From: Sebastien Bourdeauducq Date: Sun, 26 Aug 2012 19:19:34 +0000 (+0200) Subject: bus/csr: configurable data width X-Git-Tag: 24jan2021_ls180~2099^2~846 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4164fb4ac93a77cff1a777a52efe8a728bebec03;p=litex.git bus/csr: configurable data width --- diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py index f8db136a..ec9a4148 100644 --- a/migen/bank/csrgen.py +++ b/migen/bank/csrgen.py @@ -1,5 +1,5 @@ from migen.fhdl.structure import * -from migen.bus.csr import * +from migen.bus import csr from migen.bank.description import * class Bank: @@ -7,7 +7,7 @@ class Bank: self.description = description self.address = address if interface is None: - interface = Interface() + interface = csr.Interface() self.interface = interface def get_fragment(self): @@ -17,7 +17,7 @@ class Bank: sel = Signal() comb.append(sel.eq(self.interface.adr[9:] == Constant(self.address, BV(5)))) - desc_exp = expand_description(self.description, 8) + desc_exp = expand_description(self.description, csr.data_width) nbits = bits_for(len(desc_exp)-1) # Bus writes @@ -66,10 +66,10 @@ class Bank: else: raise TypeError if brcases: - sync.append(self.interface.dat_r.eq(Constant(0, BV(8)))) + sync.append(self.interface.dat_r.eq(0)) sync.append(If(sel, Case(self.interface.adr[:nbits], *brcases))) else: - comb.append(self.interface.dat_r.eq(Constant(0, BV(8)))) + comb.append(self.interface.dat_r.eq(0)) # Device access for reg in self.description: diff --git a/migen/bus/csr.py b/migen/bus/csr.py index 41750103..0bce395d 100644 --- a/migen/bus/csr.py +++ b/migen/bus/csr.py @@ -3,16 +3,15 @@ from migen.bus.simple import * from migen.bus.transactions import * from migen.sim.generic import PureSimulable -_desc = Description( - (M_TO_S, "adr", 14), - (M_TO_S, "we", 1), - (M_TO_S, "dat_w", 8), - (S_TO_M, "dat_r", 8) -) +data_width = 8 class Interface(SimpleInterface): def __init__(self): - super().__init__(_desc) + super().__init__(Description( + (M_TO_S, "adr", 14), + (M_TO_S, "we", 1), + (M_TO_S, "dat_w", data_width), + (S_TO_M, "dat_r", data_width))) class Interconnect(SimpleInterconnect): pass diff --git a/migen/bus/wishbone2csr.py b/migen/bus/wishbone2csr.py index 342f1bf5..b8018662 100644 --- a/migen/bus/wishbone2csr.py +++ b/migen/bus/wishbone2csr.py @@ -11,7 +11,7 @@ class WB2CSR: def get_fragment(self): sync = [ self.csr.we.eq(0), - self.csr.dat_w.eq(self.wishbone.dat_w[:8]), + self.csr.dat_w.eq(self.wishbone.dat_w[:csr.data_width]), self.csr.adr.eq(self.wishbone.adr[:14]), self.wishbone.dat_r.eq(self.csr.dat_r) ]