From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 20 Feb 2020 19:48:19 +0000 (+0000)
Subject: add Makefile3
X-Git-Tag: partial-core-ls180-gdsii~232
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=416b6e29f4ee79c19db1344fb3201fa42f7b2e78;p=soclayout.git

add Makefile3
---

diff --git a/Makefile3 b/Makefile3
new file mode 100755
index 0000000..10cf761
--- /dev/null
+++ b/Makefile3
@@ -0,0 +1,25 @@
+# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
+
+        LOGICAL_SYNTHESIS = Yosys
+       PHYSICAL_SYNTHESIS = Coriolis
+               DESIGN_KIT = sxlib
+
+#           YOSYS_FLATTEN = Yes
+            USE_CLOCKTREE = Yes
+                USE_DEBUG = No
+                 USE_KITE = No
+
+                 NETLISTS = $(shell cat nets3.txt)
+
+
+ include ./mk/design-flow.mk
+
+
+blif:      test_part_add.blif
+vst:       test_part_add.vst
+layout:    test_part_add_cts_r.ap
+gds:       test_part_add_cts_r.gds
+
+lvx:       lvx-test_part_add_cts_r
+druc:      druc-test_part_add_cts_r
+view:      cgt-test_part_add_cts_r
diff --git a/examples/test_part_add.py b/examples/test_part_add.py
new file mode 100644
index 0000000..560db8d
--- /dev/null
+++ b/examples/test_part_add.py
@@ -0,0 +1,57 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: LGPL-2.1-or-later
+# See Notices.txt for copyright information
+
+from nmigen import Signal, Module, Elaboratable
+from nmigen.cli import rtlil
+
+from ieee754.part.partsig import PartitionedSignal
+
+def create_ilang(dut, traces, test_name):
+    vl = rtlil.convert(dut, ports=traces, name=test_name)
+    with open("%s.il" % test_name, "w") as f:
+        f.write(vl)
+
+
+
+class TestAddMod(Elaboratable):
+    def __init__(self, width, partpoints):
+        self.partpoints = partpoints
+        self.a = PartitionedSignal(partpoints, width)
+        self.b = PartitionedSignal(partpoints, width)
+        self.add_output = Signal(width)
+        self.le_output = Signal(len(partpoints)+1)
+        self.mux_sel = Signal(len(partpoints)+1)
+        self.mux_out = Signal(width)
+        self.carry_in = Signal(len(partpoints)+1)
+        self.add_carry_out = Signal(len(partpoints)+1)
+        self.sub_carry_out = Signal(len(partpoints)+1)
+        self.neg_output = Signal(width)
+
+    def elaborate(self, platform):
+        m = Module()
+        comb = m.d.comb
+        sync = m.d.sync
+        self.a.set_module(m)
+        self.b.set_module(m)
+        # add
+        add_out, add_carry = self.a.add_op(self.a, self.b,
+                                           self.carry_in)
+        sync += self.add_output.eq(add_out)
+        sync += self.add_carry_out.eq(add_carry)
+
+        return m
+if __name__ == '__main__':
+    width = 16
+    pmask = Signal(4)  # divide into 4-bits
+    module = TestAddMod(width, pmask)
+
+    create_ilang(module,
+                           [pmask,
+                            module.a.sig,
+                            module.b.sig,
+                            module.add_output,
+                            module.carry_in,
+                            module.add_carry_out,
+                           ],
+                           "test_part_add")
diff --git a/nets3.txt b/nets3.txt
new file mode 100644
index 0000000..82796b0
--- /dev/null
+++ b/nets3.txt
@@ -0,0 +1,3 @@
+test_part_add
+ripple
+add1