From: Jan Beulich Date: Tue, 24 Jul 2018 07:46:27 +0000 (+0200) Subject: x86-64: correct AVX512F vcvtsi2s{d,s} handling X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4174bfff8a88f21659446cf631dbbbad615b4a9e;p=binutils-gdb.git x86-64: correct AVX512F vcvtsi2s{d,s} handling Just like for their AVX counterparts and CVTSI2S{D,S}, a memory source here is ambiguous and hence - in source files should be qualified with a suitable suffix or operand size specifier (not doing so is an error in Intel mode, and will gain a diagnostic in AT&T mode in the future), - in disassembly should be properly suffixed (the Intel operand size specifiers were emitted correctly already). --- diff --git a/gas/ChangeLog b/gas/ChangeLog index c96e9eab4e5..7fb92597f09 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,17 @@ +2018-07-24 Jan Beulich + + * config/tc-i386.c (check_VecOperands): Handle EVEXLIG when + deriving i.memshift. + * testsuite/gas/i386/cvtsi2sX.s, testsuite/gas/i386/cvtsi2sX.l: + New. + * testsuite/gas/i386/i386.exp: Run new test. + * testsuite/gas/i386/avx512f.d, + testsuite/gas/i386/evex-lig256.d, + testsuite/gas/i386/evex-lig512.d,, + testsuite/gas/i386/x86-64-avx512f.d, + testsuite/gas/i386/x86-64-evex-lig256.d, + testsuite/gas/i386/x86-64-evex-lig512.d: Adjust expectations. + 2018-07-23 H.J. Lu * testsuite/gas/i386/inval-avx512f.s: Add a test for missing diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 8768d688dd3..81643a73ac4 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -5256,14 +5256,17 @@ check_VecOperands (const insn_template *t) for (op = 0; op < i.operands; op++) if (operand_type_check (i.types[op], anymem)) { - if (t->operand_types[op].bitfield.xmmword - + t->operand_types[op].bitfield.ymmword - + t->operand_types[op].bitfield.zmmword <= 1) + if (t->opcode_modifier.evex == EVEXLIG) + i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); + else if (t->operand_types[op].bitfield.xmmword + + t->operand_types[op].bitfield.ymmword + + t->operand_types[op].bitfield.zmmword <= 1) type = &t->operand_types[op]; else if (!i.types[op].bitfield.unspecified) type = &i.types[op]; } - else if (i.types[op].bitfield.regsimd) + else if (i.types[op].bitfield.regsimd + && t->opcode_modifier.evex != EVEXLIG) { if (i.types[op].bitfield.zmmword) i.memshift = 6; diff --git a/gas/testsuite/gas/i386/avx512f.d b/gas/testsuite/gas/i386/avx512f.d index 522b1e59cf4..01f4e83ce67 100644 --- a/gas/testsuite/gas/i386/avx512f.d +++ b/gas/testsuite/gas/i386/avx512f.d @@ -5903,12 +5903,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 f1 7e 08 79 aa fc fd ff ff vcvtss2usi -0x204\(%edx\),%ebp [ ]*[a-f0-9]+: 62 f1 57 08 7b f0 vcvtusi2sd %eax,%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 57 08 7b f5 vcvtusi2sd %ebp,%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 08 7b 31 vcvtusi2sd \(%ecx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 08 7b b4 f4 c0 1d fe ff vcvtusi2sd -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 08 7b 72 7f vcvtusi2sd 0x1fc\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 08 7b b2 00 02 00 00 vcvtusi2sd 0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 08 7b 72 80 vcvtusi2sd -0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 08 7b b2 fc fd ff ff vcvtusi2sd -0x204\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 08 7b 31 vcvtusi2sdl \(%ecx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 08 7b b4 f4 c0 1d fe ff vcvtusi2sdl -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 08 7b 72 7f vcvtusi2sdl 0x1fc\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 08 7b b2 00 02 00 00 vcvtusi2sdl 0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 08 7b 72 80 vcvtusi2sdl -0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 08 7b b2 fc fd ff ff vcvtusi2sdl -0x204\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 08 7b f0 vcvtusi2ss %eax,%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 18 7b f0 vcvtusi2ss %eax,\{rn-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 58 7b f0 vcvtusi2ss %eax,\{ru-sae\},%xmm5,%xmm6 @@ -5919,12 +5919,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 f1 56 58 7b f5 vcvtusi2ss %ebp,\{ru-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 38 7b f5 vcvtusi2ss %ebp,\{rd-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 78 7b f5 vcvtusi2ss %ebp,\{rz-sae\},%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 08 7b 31 vcvtusi2ss \(%ecx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 08 7b b4 f4 c0 1d fe ff vcvtusi2ss -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 08 7b 72 7f vcvtusi2ss 0x1fc\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 08 7b b2 00 02 00 00 vcvtusi2ss 0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 08 7b 72 80 vcvtusi2ss -0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 08 7b b2 fc fd ff ff vcvtusi2ss -0x204\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 08 7b 31 vcvtusi2ssl \(%ecx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 08 7b b4 f4 c0 1d fe ff vcvtusi2ssl -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 08 7b 72 7f vcvtusi2ssl 0x1fc\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 08 7b b2 00 02 00 00 vcvtusi2ssl 0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 08 7b 72 80 vcvtusi2ssl -0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 08 7b b2 fc fd ff ff vcvtusi2ssl -0x204\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f2 d5 48 2c f4 vscalefpd %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+: 62 f2 d5 4f 2c f4 vscalefpd %zmm4,%zmm5,%zmm6\{%k7\} [ ]*[a-f0-9]+: 62 f2 d5 cf 2c f4 vscalefpd %zmm4,%zmm5,%zmm6\{%k7\}\{z\} @@ -12546,12 +12546,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 f1 7e 08 79 aa fc fd ff ff vcvtss2usi -0x204\(%edx\),%ebp [ ]*[a-f0-9]+: 62 f1 57 08 7b f0 vcvtusi2sd %eax,%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 57 08 7b f5 vcvtusi2sd %ebp,%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 08 7b 31 vcvtusi2sd \(%ecx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 08 7b b4 f4 c0 1d fe ff vcvtusi2sd -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 08 7b 72 7f vcvtusi2sd 0x1fc\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 08 7b b2 00 02 00 00 vcvtusi2sd 0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 08 7b 72 80 vcvtusi2sd -0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 08 7b b2 fc fd ff ff vcvtusi2sd -0x204\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 08 7b 31 vcvtusi2sdl \(%ecx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 08 7b b4 f4 c0 1d fe ff vcvtusi2sdl -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 08 7b 72 7f vcvtusi2sdl 0x1fc\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 08 7b b2 00 02 00 00 vcvtusi2sdl 0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 08 7b 72 80 vcvtusi2sdl -0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 08 7b b2 fc fd ff ff vcvtusi2sdl -0x204\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 08 7b f0 vcvtusi2ss %eax,%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 18 7b f0 vcvtusi2ss %eax,\{rn-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 58 7b f0 vcvtusi2ss %eax,\{ru-sae\},%xmm5,%xmm6 @@ -12562,12 +12562,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 f1 56 58 7b f5 vcvtusi2ss %ebp,\{ru-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 38 7b f5 vcvtusi2ss %ebp,\{rd-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 78 7b f5 vcvtusi2ss %ebp,\{rz-sae\},%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 08 7b 31 vcvtusi2ss \(%ecx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 08 7b b4 f4 c0 1d fe ff vcvtusi2ss -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 08 7b 72 7f vcvtusi2ss 0x1fc\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 08 7b b2 00 02 00 00 vcvtusi2ss 0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 08 7b 72 80 vcvtusi2ss -0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 08 7b b2 fc fd ff ff vcvtusi2ss -0x204\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 08 7b 31 vcvtusi2ssl \(%ecx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 08 7b b4 f4 c0 1d fe ff vcvtusi2ssl -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 08 7b 72 7f vcvtusi2ssl 0x1fc\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 08 7b b2 00 02 00 00 vcvtusi2ssl 0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 08 7b 72 80 vcvtusi2ssl -0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 08 7b b2 fc fd ff ff vcvtusi2ssl -0x204\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f2 d5 48 2c f4 vscalefpd %zmm4,%zmm5,%zmm6 [ ]*[a-f0-9]+: 62 f2 d5 4f 2c f4 vscalefpd %zmm4,%zmm5,%zmm6\{%k7\} [ ]*[a-f0-9]+: 62 f2 d5 cf 2c f4 vscalefpd %zmm4,%zmm5,%zmm6\{%k7\}\{z\} diff --git a/gas/testsuite/gas/i386/cvtsi2sX.l b/gas/testsuite/gas/i386/cvtsi2sX.l new file mode 100644 index 00000000000..77a7b31eb13 --- /dev/null +++ b/gas/testsuite/gas/i386/cvtsi2sX.l @@ -0,0 +1,9 @@ +.*: Assembler messages: +.*:4: Error: ambiguous .* `cvtsi2sd' +.*:5: Error: ambiguous .* `cvtsi2ss' +.*:7: Error: ambiguous .* `vcvtsi2sd' +.*:8: Error: ambiguous .* `vcvtsi2ss' +.*:10: Error: ambiguous .* `vcvtsi2sd' +.*:11: Error: ambiguous .* `vcvtsi2ss' +.*:13: Error: ambiguous .* `vcvtusi2sd' +.*:14: Error: ambiguous .* `vcvtusi2ss' diff --git a/gas/testsuite/gas/i386/cvtsi2sX.s b/gas/testsuite/gas/i386/cvtsi2sX.s new file mode 100644 index 00000000000..f22991342a8 --- /dev/null +++ b/gas/testsuite/gas/i386/cvtsi2sX.s @@ -0,0 +1,14 @@ + .text +cvtsi2sX: + .intel_syntax noprefix + cvtsi2sd xmm0, [rax] + cvtsi2ss xmm0, [rax] + + vcvtsi2sd xmm0, xmm0, [rax] + vcvtsi2ss xmm0, xmm0, [rax] + + vcvtsi2sd xmm31, xmm31, [rax] + vcvtsi2ss xmm31, xmm31, [rax] + + vcvtusi2sd xmm0, xmm0, [rax] + vcvtusi2ss xmm0, xmm0, [rax] diff --git a/gas/testsuite/gas/i386/evex-lig256.d b/gas/testsuite/gas/i386/evex-lig256.d index 7e992586cab..79fe6f76f2a 100644 --- a/gas/testsuite/gas/i386/evex-lig256.d +++ b/gas/testsuite/gas/i386/evex-lig256.d @@ -1446,12 +1446,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 f1 7e 28 79 aa fc fd ff ff vcvtss2usi -0x204\(%edx\),%ebp [ ]*[a-f0-9]+: 62 f1 57 28 7b f0 vcvtusi2sd %eax,%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 57 28 7b f5 vcvtusi2sd %ebp,%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 28 7b 31 vcvtusi2sd \(%ecx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 28 7b b4 f4 c0 1d fe ff vcvtusi2sd -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 28 7b 72 7f vcvtusi2sd 0x1fc\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 28 7b b2 00 02 00 00 vcvtusi2sd 0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 28 7b 72 80 vcvtusi2sd -0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 28 7b b2 fc fd ff ff vcvtusi2sd -0x204\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 28 7b 31 vcvtusi2sdl \(%ecx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 28 7b b4 f4 c0 1d fe ff vcvtusi2sdl -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 28 7b 72 7f vcvtusi2sdl 0x1fc\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 28 7b b2 00 02 00 00 vcvtusi2sdl 0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 28 7b 72 80 vcvtusi2sdl -0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 28 7b b2 fc fd ff ff vcvtusi2sdl -0x204\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 28 7b f0 vcvtusi2ss %eax,%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 18 7b f0 vcvtusi2ss %eax,\{rn-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 58 7b f0 vcvtusi2ss %eax,\{ru-sae\},%xmm5,%xmm6 @@ -1462,12 +1462,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 f1 56 58 7b f5 vcvtusi2ss %ebp,\{ru-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 38 7b f5 vcvtusi2ss %ebp,\{rd-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 78 7b f5 vcvtusi2ss %ebp,\{rz-sae\},%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 28 7b 31 vcvtusi2ss \(%ecx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 28 7b b4 f4 c0 1d fe ff vcvtusi2ss -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 28 7b 72 7f vcvtusi2ss 0x1fc\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 28 7b b2 00 02 00 00 vcvtusi2ss 0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 28 7b 72 80 vcvtusi2ss -0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 28 7b b2 fc fd ff ff vcvtusi2ss -0x204\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 28 7b 31 vcvtusi2ssl \(%ecx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 28 7b b4 f4 c0 1d fe ff vcvtusi2ssl -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 28 7b 72 7f vcvtusi2ssl 0x1fc\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 28 7b b2 00 02 00 00 vcvtusi2ssl 0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 28 7b 72 80 vcvtusi2ssl -0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 28 7b b2 fc fd ff ff vcvtusi2ssl -0x204\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f2 d5 2f 2d f4 vscalefsd %xmm4,%xmm5,%xmm6\{%k7\} [ ]*[a-f0-9]+: 62 f2 d5 af 2d f4 vscalefsd %xmm4,%xmm5,%xmm6\{%k7\}\{z\} [ ]*[a-f0-9]+: 62 f2 d5 1f 2d f4 vscalefsd \{rn-sae\},%xmm4,%xmm5,%xmm6\{%k7\} @@ -2973,12 +2973,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 f1 7e 28 79 aa fc fd ff ff vcvtss2usi -0x204\(%edx\),%ebp [ ]*[a-f0-9]+: 62 f1 57 28 7b f0 vcvtusi2sd %eax,%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 57 28 7b f5 vcvtusi2sd %ebp,%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 28 7b 31 vcvtusi2sd \(%ecx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 28 7b b4 f4 c0 1d fe ff vcvtusi2sd -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 28 7b 72 7f vcvtusi2sd 0x1fc\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 28 7b b2 00 02 00 00 vcvtusi2sd 0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 28 7b 72 80 vcvtusi2sd -0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 28 7b b2 fc fd ff ff vcvtusi2sd -0x204\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 28 7b 31 vcvtusi2sdl \(%ecx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 28 7b b4 f4 c0 1d fe ff vcvtusi2sdl -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 28 7b 72 7f vcvtusi2sdl 0x1fc\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 28 7b b2 00 02 00 00 vcvtusi2sdl 0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 28 7b 72 80 vcvtusi2sdl -0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 28 7b b2 fc fd ff ff vcvtusi2sdl -0x204\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 28 7b f0 vcvtusi2ss %eax,%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 18 7b f0 vcvtusi2ss %eax,\{rn-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 58 7b f0 vcvtusi2ss %eax,\{ru-sae\},%xmm5,%xmm6 @@ -2989,12 +2989,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 f1 56 58 7b f5 vcvtusi2ss %ebp,\{ru-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 38 7b f5 vcvtusi2ss %ebp,\{rd-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 78 7b f5 vcvtusi2ss %ebp,\{rz-sae\},%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 28 7b 31 vcvtusi2ss \(%ecx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 28 7b b4 f4 c0 1d fe ff vcvtusi2ss -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 28 7b 72 7f vcvtusi2ss 0x1fc\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 28 7b b2 00 02 00 00 vcvtusi2ss 0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 28 7b 72 80 vcvtusi2ss -0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 28 7b b2 fc fd ff ff vcvtusi2ss -0x204\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 28 7b 31 vcvtusi2ssl \(%ecx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 28 7b b4 f4 c0 1d fe ff vcvtusi2ssl -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 28 7b 72 7f vcvtusi2ssl 0x1fc\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 28 7b b2 00 02 00 00 vcvtusi2ssl 0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 28 7b 72 80 vcvtusi2ssl -0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 28 7b b2 fc fd ff ff vcvtusi2ssl -0x204\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f2 d5 2f 2d f4 vscalefsd %xmm4,%xmm5,%xmm6\{%k7\} [ ]*[a-f0-9]+: 62 f2 d5 af 2d f4 vscalefsd %xmm4,%xmm5,%xmm6\{%k7\}\{z\} [ ]*[a-f0-9]+: 62 f2 d5 1f 2d f4 vscalefsd \{rn-sae\},%xmm4,%xmm5,%xmm6\{%k7\} diff --git a/gas/testsuite/gas/i386/evex-lig512.d b/gas/testsuite/gas/i386/evex-lig512.d index a3c85b837a6..a0638f04817 100644 --- a/gas/testsuite/gas/i386/evex-lig512.d +++ b/gas/testsuite/gas/i386/evex-lig512.d @@ -1446,12 +1446,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 f1 7e 48 79 aa fc fd ff ff vcvtss2usi -0x204\(%edx\),%ebp [ ]*[a-f0-9]+: 62 f1 57 48 7b f0 vcvtusi2sd %eax,%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 57 48 7b f5 vcvtusi2sd %ebp,%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 48 7b 31 vcvtusi2sd \(%ecx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 48 7b b4 f4 c0 1d fe ff vcvtusi2sd -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 48 7b 72 7f vcvtusi2sd 0x1fc\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 48 7b b2 00 02 00 00 vcvtusi2sd 0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 48 7b 72 80 vcvtusi2sd -0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 48 7b b2 fc fd ff ff vcvtusi2sd -0x204\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 48 7b 31 vcvtusi2sdl \(%ecx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 48 7b b4 f4 c0 1d fe ff vcvtusi2sdl -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 48 7b 72 7f vcvtusi2sdl 0x1fc\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 48 7b b2 00 02 00 00 vcvtusi2sdl 0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 48 7b 72 80 vcvtusi2sdl -0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 48 7b b2 fc fd ff ff vcvtusi2sdl -0x204\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 48 7b f0 vcvtusi2ss %eax,%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 18 7b f0 vcvtusi2ss %eax,\{rn-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 58 7b f0 vcvtusi2ss %eax,\{ru-sae\},%xmm5,%xmm6 @@ -1462,12 +1462,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 f1 56 58 7b f5 vcvtusi2ss %ebp,\{ru-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 38 7b f5 vcvtusi2ss %ebp,\{rd-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 78 7b f5 vcvtusi2ss %ebp,\{rz-sae\},%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 48 7b 31 vcvtusi2ss \(%ecx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 48 7b b4 f4 c0 1d fe ff vcvtusi2ss -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 48 7b 72 7f vcvtusi2ss 0x1fc\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 48 7b b2 00 02 00 00 vcvtusi2ss 0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 48 7b 72 80 vcvtusi2ss -0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 48 7b b2 fc fd ff ff vcvtusi2ss -0x204\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 48 7b 31 vcvtusi2ssl \(%ecx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 48 7b b4 f4 c0 1d fe ff vcvtusi2ssl -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 48 7b 72 7f vcvtusi2ssl 0x1fc\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 48 7b b2 00 02 00 00 vcvtusi2ssl 0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 48 7b 72 80 vcvtusi2ssl -0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 48 7b b2 fc fd ff ff vcvtusi2ssl -0x204\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f2 d5 4f 2d f4 vscalefsd %xmm4,%xmm5,%xmm6\{%k7\} [ ]*[a-f0-9]+: 62 f2 d5 cf 2d f4 vscalefsd %xmm4,%xmm5,%xmm6\{%k7\}\{z\} [ ]*[a-f0-9]+: 62 f2 d5 1f 2d f4 vscalefsd \{rn-sae\},%xmm4,%xmm5,%xmm6\{%k7\} @@ -2973,12 +2973,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 f1 7e 48 79 aa fc fd ff ff vcvtss2usi -0x204\(%edx\),%ebp [ ]*[a-f0-9]+: 62 f1 57 48 7b f0 vcvtusi2sd %eax,%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 57 48 7b f5 vcvtusi2sd %ebp,%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 48 7b 31 vcvtusi2sd \(%ecx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 48 7b b4 f4 c0 1d fe ff vcvtusi2sd -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 48 7b 72 7f vcvtusi2sd 0x1fc\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 48 7b b2 00 02 00 00 vcvtusi2sd 0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 48 7b 72 80 vcvtusi2sd -0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 57 48 7b b2 fc fd ff ff vcvtusi2sd -0x204\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 48 7b 31 vcvtusi2sdl \(%ecx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 48 7b b4 f4 c0 1d fe ff vcvtusi2sdl -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 48 7b 72 7f vcvtusi2sdl 0x1fc\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 48 7b b2 00 02 00 00 vcvtusi2sdl 0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 48 7b 72 80 vcvtusi2sdl -0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 57 48 7b b2 fc fd ff ff vcvtusi2sdl -0x204\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 48 7b f0 vcvtusi2ss %eax,%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 18 7b f0 vcvtusi2ss %eax,\{rn-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 58 7b f0 vcvtusi2ss %eax,\{ru-sae\},%xmm5,%xmm6 @@ -2989,12 +2989,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 f1 56 58 7b f5 vcvtusi2ss %ebp,\{ru-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 38 7b f5 vcvtusi2ss %ebp,\{rd-sae\},%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f1 56 78 7b f5 vcvtusi2ss %ebp,\{rz-sae\},%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 48 7b 31 vcvtusi2ss \(%ecx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 48 7b b4 f4 c0 1d fe ff vcvtusi2ss -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 48 7b 72 7f vcvtusi2ss 0x1fc\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 48 7b b2 00 02 00 00 vcvtusi2ss 0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 48 7b 72 80 vcvtusi2ss -0x200\(%edx\),%xmm5,%xmm6 -[ ]*[a-f0-9]+: 62 f1 56 48 7b b2 fc fd ff ff vcvtusi2ss -0x204\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 48 7b 31 vcvtusi2ssl \(%ecx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 48 7b b4 f4 c0 1d fe ff vcvtusi2ssl -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 48 7b 72 7f vcvtusi2ssl 0x1fc\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 48 7b b2 00 02 00 00 vcvtusi2ssl 0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 48 7b 72 80 vcvtusi2ssl -0x200\(%edx\),%xmm5,%xmm6 +[ ]*[a-f0-9]+: 62 f1 56 48 7b b2 fc fd ff ff vcvtusi2ssl -0x204\(%edx\),%xmm5,%xmm6 [ ]*[a-f0-9]+: 62 f2 d5 4f 2d f4 vscalefsd %xmm4,%xmm5,%xmm6\{%k7\} [ ]*[a-f0-9]+: 62 f2 d5 cf 2d f4 vscalefsd %xmm4,%xmm5,%xmm6\{%k7\}\{z\} [ ]*[a-f0-9]+: 62 f2 d5 1f 2d f4 vscalefsd \{rn-sae\},%xmm4,%xmm5,%xmm6\{%k7\} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 9cc927a9626..eb51c450085 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -654,6 +654,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-nops-5" run_dump_test "x86-64-nops-5-k8" run_dump_test "x86-64-nops-7" + run_list_test "cvtsi2sX" run_dump_test "x86-64-sse4_1" run_dump_test "x86-64-sse4_1-intel" run_dump_test "x86-64-sse4_2" diff --git a/gas/testsuite/gas/i386/x86-64-avx512f.d b/gas/testsuite/gas/i386/x86-64-avx512f.d index 2db0b3e0f94..652bfc6ab12 100644 --- a/gas/testsuite/gas/i386/x86-64-avx512f.d +++ b/gas/testsuite/gas/i386/x86-64-avx512f.d @@ -2456,12 +2456,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 61 17 00 2a f0 vcvtsi2sd %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 17 00 2a f5 vcvtsi2sd %ebp,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 17 00 2a f5 vcvtsi2sd %r13d,%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 2a 31 vcvtsi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 17 00 2a b4 f0 23 01 00 00 vcvtsi2sd 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 2a 72 7f vcvtsi2sd 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 2a b2 00 02 00 00 vcvtsi2sd 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 2a 72 80 vcvtsi2sd -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 2a b2 fc fd ff ff vcvtsi2sd -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 2a 31 vcvtsi2sdl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 17 00 2a b4 f0 23 01 00 00 vcvtsi2sdl 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 2a 72 7f vcvtsi2sdl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 2a b2 00 02 00 00 vcvtsi2sdl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 2a 72 80 vcvtsi2sdl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 2a b2 fc fd ff ff vcvtsi2sdl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 00 2a f0 vcvtsi2sd %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 10 2a f0 vcvtsi2sd %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 50 2a f0 vcvtsi2sd %rax,\{ru-sae\},%xmm29,%xmm30 @@ -2472,12 +2472,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 97 50 2a f0 vcvtsi2sd %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 30 2a f0 vcvtsi2sd %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 70 2a f0 vcvtsi2sd %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 2a 31 vcvtsi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 97 00 2a b4 f0 23 01 00 00 vcvtsi2sd 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 2a 72 7f vcvtsi2sd 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 2a b2 00 04 00 00 vcvtsi2sd 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 2a 72 80 vcvtsi2sd -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 2a b2 f8 fb ff ff vcvtsi2sd -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 2a 31 vcvtsi2sdq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 97 00 2a b4 f0 23 01 00 00 vcvtsi2sdq 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 2a 72 7f vcvtsi2sdq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 2a b2 00 04 00 00 vcvtsi2sdq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 2a 72 80 vcvtsi2sdq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 2a b2 f8 fb ff ff vcvtsi2sdq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 00 2a f0 vcvtsi2ss %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 10 2a f0 vcvtsi2ss %eax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 50 2a f0 vcvtsi2ss %eax,\{ru-sae\},%xmm29,%xmm30 @@ -2493,12 +2493,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 16 50 2a f5 vcvtsi2ss %r13d,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 30 2a f5 vcvtsi2ss %r13d,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 70 2a f5 vcvtsi2ss %r13d,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 2a 31 vcvtsi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 16 00 2a b4 f0 23 01 00 00 vcvtsi2ss 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 2a 72 7f vcvtsi2ss 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 2a b2 00 02 00 00 vcvtsi2ss 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 2a 72 80 vcvtsi2ss -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 2a b2 fc fd ff ff vcvtsi2ss -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 2a 31 vcvtsi2ssl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 16 00 2a b4 f0 23 01 00 00 vcvtsi2ssl 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 2a 72 7f vcvtsi2ssl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 2a b2 00 02 00 00 vcvtsi2ssl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 2a 72 80 vcvtsi2ssl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 2a b2 fc fd ff ff vcvtsi2ssl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 00 2a f0 vcvtsi2ss %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 10 2a f0 vcvtsi2ss %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 50 2a f0 vcvtsi2ss %rax,\{ru-sae\},%xmm29,%xmm30 @@ -2509,12 +2509,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 96 50 2a f0 vcvtsi2ss %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 30 2a f0 vcvtsi2ss %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 70 2a f0 vcvtsi2ss %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 2a 31 vcvtsi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 96 00 2a b4 f0 23 01 00 00 vcvtsi2ss 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 2a 72 7f vcvtsi2ss 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 2a b2 00 04 00 00 vcvtsi2ss 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 2a 72 80 vcvtsi2ss -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 2a b2 f8 fb ff ff vcvtsi2ss -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 2a 31 vcvtsi2ssq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 96 00 2a b4 f0 23 01 00 00 vcvtsi2ssq 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 2a 72 7f vcvtsi2ssq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 2a b2 00 04 00 00 vcvtsi2ssq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 2a 72 80 vcvtsi2ssq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 2a b2 f8 fb ff ff vcvtsi2ssq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 01 16 07 5a f4 vcvtss2sd %xmm28,%xmm29,%xmm30\{%k7\} [ ]*[a-f0-9]+: 62 01 16 87 5a f4 vcvtss2sd %xmm28,%xmm29,%xmm30\{%k7\}\{z\} [ ]*[a-f0-9]+: 62 01 16 17 5a f4 vcvtss2sd \{sae\},%xmm28,%xmm29,%xmm30\{%k7\} @@ -6197,12 +6197,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 61 17 00 7b f0 vcvtusi2sd %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 17 00 7b f5 vcvtusi2sd %ebp,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 17 00 7b f5 vcvtusi2sd %r13d,%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 7b 31 vcvtusi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 17 00 7b b4 f0 23 01 00 00 vcvtusi2sd 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 7b 72 7f vcvtusi2sd 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 7b b2 00 02 00 00 vcvtusi2sd 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 7b 72 80 vcvtusi2sd -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 7b b2 fc fd ff ff vcvtusi2sd -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 7b 31 vcvtusi2sdl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 17 00 7b b4 f0 23 01 00 00 vcvtusi2sdl 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 7b 72 7f vcvtusi2sdl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 7b b2 00 02 00 00 vcvtusi2sdl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 7b 72 80 vcvtusi2sdl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 7b b2 fc fd ff ff vcvtusi2sdl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 00 7b f0 vcvtusi2sd %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 10 7b f0 vcvtusi2sd %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 50 7b f0 vcvtusi2sd %rax,\{ru-sae\},%xmm29,%xmm30 @@ -6213,12 +6213,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 97 50 7b f0 vcvtusi2sd %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 30 7b f0 vcvtusi2sd %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 70 7b f0 vcvtusi2sd %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 7b 31 vcvtusi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 97 00 7b b4 f0 23 01 00 00 vcvtusi2sd 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 7b 72 7f vcvtusi2sd 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 7b b2 00 04 00 00 vcvtusi2sd 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 7b 72 80 vcvtusi2sd -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 7b b2 f8 fb ff ff vcvtusi2sd -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 7b 31 vcvtusi2sdq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 97 00 7b b4 f0 23 01 00 00 vcvtusi2sdq 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 7b 72 7f vcvtusi2sdq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 7b b2 00 04 00 00 vcvtusi2sdq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 7b 72 80 vcvtusi2sdq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 7b b2 f8 fb ff ff vcvtusi2sdq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 00 7b f0 vcvtusi2ss %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 10 7b f0 vcvtusi2ss %eax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 50 7b f0 vcvtusi2ss %eax,\{ru-sae\},%xmm29,%xmm30 @@ -6234,12 +6234,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 16 50 7b f5 vcvtusi2ss %r13d,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 30 7b f5 vcvtusi2ss %r13d,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 70 7b f5 vcvtusi2ss %r13d,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 7b 31 vcvtusi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 16 00 7b b4 f0 23 01 00 00 vcvtusi2ss 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 7b 72 7f vcvtusi2ss 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 7b b2 00 02 00 00 vcvtusi2ss 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 7b 72 80 vcvtusi2ss -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 7b b2 fc fd ff ff vcvtusi2ss -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 7b 31 vcvtusi2ssl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 16 00 7b b4 f0 23 01 00 00 vcvtusi2ssl 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 7b 72 7f vcvtusi2ssl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 7b b2 00 02 00 00 vcvtusi2ssl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 7b 72 80 vcvtusi2ssl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 7b b2 fc fd ff ff vcvtusi2ssl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 00 7b f0 vcvtusi2ss %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 10 7b f0 vcvtusi2ss %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 50 7b f0 vcvtusi2ss %rax,\{ru-sae\},%xmm29,%xmm30 @@ -6250,12 +6250,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 96 50 7b f0 vcvtusi2ss %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 30 7b f0 vcvtusi2ss %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 70 7b f0 vcvtusi2ss %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 7b 31 vcvtusi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 96 00 7b b4 f0 23 01 00 00 vcvtusi2ss 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 7b 72 7f vcvtusi2ss 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 7b b2 00 04 00 00 vcvtusi2ss 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 7b 72 80 vcvtusi2ss -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 7b b2 f8 fb ff ff vcvtusi2ss -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 7b 31 vcvtusi2ssq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 96 00 7b b4 f0 23 01 00 00 vcvtusi2ssq 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 7b 72 7f vcvtusi2ssq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 7b b2 00 04 00 00 vcvtusi2ssq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 7b 72 80 vcvtusi2ssq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 7b b2 f8 fb ff ff vcvtusi2ssq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 02 95 40 2c f4 vscalefpd %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+: 62 02 95 47 2c f4 vscalefpd %zmm28,%zmm29,%zmm30\{%k7\} [ ]*[a-f0-9]+: 62 02 95 c7 2c f4 vscalefpd %zmm28,%zmm29,%zmm30\{%k7\}\{z\} @@ -9477,12 +9477,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 61 17 00 2a f0 vcvtsi2sd %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 17 00 2a f5 vcvtsi2sd %ebp,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 17 00 2a f5 vcvtsi2sd %r13d,%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 2a 31 vcvtsi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 17 00 2a b4 f0 34 12 00 00 vcvtsi2sd 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 2a 72 7f vcvtsi2sd 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 2a b2 00 02 00 00 vcvtsi2sd 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 2a 72 80 vcvtsi2sd -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 2a b2 fc fd ff ff vcvtsi2sd -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 2a 31 vcvtsi2sdl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 17 00 2a b4 f0 34 12 00 00 vcvtsi2sdl 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 2a 72 7f vcvtsi2sdl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 2a b2 00 02 00 00 vcvtsi2sdl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 2a 72 80 vcvtsi2sdl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 2a b2 fc fd ff ff vcvtsi2sdl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 00 2a f0 vcvtsi2sd %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 10 2a f0 vcvtsi2sd %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 50 2a f0 vcvtsi2sd %rax,\{ru-sae\},%xmm29,%xmm30 @@ -9493,12 +9493,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 97 50 2a f0 vcvtsi2sd %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 30 2a f0 vcvtsi2sd %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 70 2a f0 vcvtsi2sd %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 2a 31 vcvtsi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 97 00 2a b4 f0 34 12 00 00 vcvtsi2sd 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 2a 72 7f vcvtsi2sd 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 2a b2 00 04 00 00 vcvtsi2sd 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 2a 72 80 vcvtsi2sd -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 2a b2 f8 fb ff ff vcvtsi2sd -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 2a 31 vcvtsi2sdq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 97 00 2a b4 f0 34 12 00 00 vcvtsi2sdq 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 2a 72 7f vcvtsi2sdq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 2a b2 00 04 00 00 vcvtsi2sdq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 2a 72 80 vcvtsi2sdq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 2a b2 f8 fb ff ff vcvtsi2sdq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 00 2a f0 vcvtsi2ss %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 10 2a f0 vcvtsi2ss %eax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 50 2a f0 vcvtsi2ss %eax,\{ru-sae\},%xmm29,%xmm30 @@ -9514,12 +9514,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 16 50 2a f5 vcvtsi2ss %r13d,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 30 2a f5 vcvtsi2ss %r13d,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 70 2a f5 vcvtsi2ss %r13d,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 2a 31 vcvtsi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 16 00 2a b4 f0 34 12 00 00 vcvtsi2ss 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 2a 72 7f vcvtsi2ss 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 2a b2 00 02 00 00 vcvtsi2ss 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 2a 72 80 vcvtsi2ss -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 2a b2 fc fd ff ff vcvtsi2ss -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 2a 31 vcvtsi2ssl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 16 00 2a b4 f0 34 12 00 00 vcvtsi2ssl 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 2a 72 7f vcvtsi2ssl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 2a b2 00 02 00 00 vcvtsi2ssl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 2a 72 80 vcvtsi2ssl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 2a b2 fc fd ff ff vcvtsi2ssl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 00 2a f0 vcvtsi2ss %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 10 2a f0 vcvtsi2ss %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 50 2a f0 vcvtsi2ss %rax,\{ru-sae\},%xmm29,%xmm30 @@ -9530,12 +9530,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 96 50 2a f0 vcvtsi2ss %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 30 2a f0 vcvtsi2ss %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 70 2a f0 vcvtsi2ss %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 2a 31 vcvtsi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 96 00 2a b4 f0 34 12 00 00 vcvtsi2ss 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 2a 72 7f vcvtsi2ss 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 2a b2 00 04 00 00 vcvtsi2ss 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 2a 72 80 vcvtsi2ss -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 2a b2 f8 fb ff ff vcvtsi2ss -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 2a 31 vcvtsi2ssq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 96 00 2a b4 f0 34 12 00 00 vcvtsi2ssq 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 2a 72 7f vcvtsi2ssq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 2a b2 00 04 00 00 vcvtsi2ssq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 2a 72 80 vcvtsi2ssq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 2a b2 f8 fb ff ff vcvtsi2ssq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 01 16 07 5a f4 vcvtss2sd %xmm28,%xmm29,%xmm30\{%k7\} [ ]*[a-f0-9]+: 62 01 16 87 5a f4 vcvtss2sd %xmm28,%xmm29,%xmm30\{%k7\}\{z\} [ ]*[a-f0-9]+: 62 01 16 17 5a f4 vcvtss2sd \{sae\},%xmm28,%xmm29,%xmm30\{%k7\} @@ -13218,12 +13218,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 61 17 00 7b f0 vcvtusi2sd %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 17 00 7b f5 vcvtusi2sd %ebp,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 17 00 7b f5 vcvtusi2sd %r13d,%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 7b 31 vcvtusi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 17 00 7b b4 f0 34 12 00 00 vcvtusi2sd 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 7b 72 7f vcvtusi2sd 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 7b b2 00 02 00 00 vcvtusi2sd 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 7b 72 80 vcvtusi2sd -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 00 7b b2 fc fd ff ff vcvtusi2sd -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 7b 31 vcvtusi2sdl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 17 00 7b b4 f0 34 12 00 00 vcvtusi2sdl 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 7b 72 7f vcvtusi2sdl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 7b b2 00 02 00 00 vcvtusi2sdl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 7b 72 80 vcvtusi2sdl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 00 7b b2 fc fd ff ff vcvtusi2sdl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 00 7b f0 vcvtusi2sd %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 10 7b f0 vcvtusi2sd %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 50 7b f0 vcvtusi2sd %rax,\{ru-sae\},%xmm29,%xmm30 @@ -13234,12 +13234,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 97 50 7b f0 vcvtusi2sd %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 30 7b f0 vcvtusi2sd %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 70 7b f0 vcvtusi2sd %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 7b 31 vcvtusi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 97 00 7b b4 f0 34 12 00 00 vcvtusi2sd 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 7b 72 7f vcvtusi2sd 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 7b b2 00 04 00 00 vcvtusi2sd 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 7b 72 80 vcvtusi2sd -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 00 7b b2 f8 fb ff ff vcvtusi2sd -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 7b 31 vcvtusi2sdq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 97 00 7b b4 f0 34 12 00 00 vcvtusi2sdq 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 7b 72 7f vcvtusi2sdq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 7b b2 00 04 00 00 vcvtusi2sdq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 7b 72 80 vcvtusi2sdq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 00 7b b2 f8 fb ff ff vcvtusi2sdq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 00 7b f0 vcvtusi2ss %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 10 7b f0 vcvtusi2ss %eax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 50 7b f0 vcvtusi2ss %eax,\{ru-sae\},%xmm29,%xmm30 @@ -13255,12 +13255,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 16 50 7b f5 vcvtusi2ss %r13d,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 30 7b f5 vcvtusi2ss %r13d,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 70 7b f5 vcvtusi2ss %r13d,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 7b 31 vcvtusi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 16 00 7b b4 f0 34 12 00 00 vcvtusi2ss 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 7b 72 7f vcvtusi2ss 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 7b b2 00 02 00 00 vcvtusi2ss 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 7b 72 80 vcvtusi2ss -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 00 7b b2 fc fd ff ff vcvtusi2ss -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 7b 31 vcvtusi2ssl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 16 00 7b b4 f0 34 12 00 00 vcvtusi2ssl 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 7b 72 7f vcvtusi2ssl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 7b b2 00 02 00 00 vcvtusi2ssl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 7b 72 80 vcvtusi2ssl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 00 7b b2 fc fd ff ff vcvtusi2ssl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 00 7b f0 vcvtusi2ss %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 10 7b f0 vcvtusi2ss %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 50 7b f0 vcvtusi2ss %rax,\{ru-sae\},%xmm29,%xmm30 @@ -13271,12 +13271,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 96 50 7b f0 vcvtusi2ss %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 30 7b f0 vcvtusi2ss %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 70 7b f0 vcvtusi2ss %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 7b 31 vcvtusi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 96 00 7b b4 f0 34 12 00 00 vcvtusi2ss 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 7b 72 7f vcvtusi2ss 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 7b b2 00 04 00 00 vcvtusi2ss 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 7b 72 80 vcvtusi2ss -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 00 7b b2 f8 fb ff ff vcvtusi2ss -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 7b 31 vcvtusi2ssq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 96 00 7b b4 f0 34 12 00 00 vcvtusi2ssq 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 7b 72 7f vcvtusi2ssq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 7b b2 00 04 00 00 vcvtusi2ssq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 7b 72 80 vcvtusi2ssq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 00 7b b2 f8 fb ff ff vcvtusi2ssq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 02 95 40 2c f4 vscalefpd %zmm28,%zmm29,%zmm30 [ ]*[a-f0-9]+: 62 02 95 47 2c f4 vscalefpd %zmm28,%zmm29,%zmm30\{%k7\} [ ]*[a-f0-9]+: 62 02 95 c7 2c f4 vscalefpd %zmm28,%zmm29,%zmm30\{%k7\}\{z\} diff --git a/gas/testsuite/gas/i386/x86-64-evex-lig256.d b/gas/testsuite/gas/i386/x86-64-evex-lig256.d index 7f76350e6bd..2127cbc1363 100644 --- a/gas/testsuite/gas/i386/x86-64-evex-lig256.d +++ b/gas/testsuite/gas/i386/x86-64-evex-lig256.d @@ -840,12 +840,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 61 17 20 2a f0 vcvtsi2sd %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 17 20 2a f5 vcvtsi2sd %ebp,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 17 20 2a f5 vcvtsi2sd %r13d,%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 2a 31 vcvtsi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 17 20 2a b4 f0 23 01 00 00 vcvtsi2sd 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 2a 72 7f vcvtsi2sd 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 2a b2 00 02 00 00 vcvtsi2sd 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 2a 72 80 vcvtsi2sd -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 2a b2 fc fd ff ff vcvtsi2sd -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 2a 31 vcvtsi2sdl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 17 20 2a b4 f0 23 01 00 00 vcvtsi2sdl 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 2a 72 7f vcvtsi2sdl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 2a b2 00 02 00 00 vcvtsi2sdl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 2a 72 80 vcvtsi2sdl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 2a b2 fc fd ff ff vcvtsi2sdl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 20 2a f0 vcvtsi2sd %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 10 2a f0 vcvtsi2sd %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 50 2a f0 vcvtsi2sd %rax,\{ru-sae\},%xmm29,%xmm30 @@ -856,12 +856,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 97 50 2a f0 vcvtsi2sd %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 30 2a f0 vcvtsi2sd %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 70 2a f0 vcvtsi2sd %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 2a 31 vcvtsi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 97 20 2a b4 f0 23 01 00 00 vcvtsi2sd 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 2a 72 7f vcvtsi2sd 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 2a b2 00 04 00 00 vcvtsi2sd 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 2a 72 80 vcvtsi2sd -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 2a b2 f8 fb ff ff vcvtsi2sd -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 2a 31 vcvtsi2sdq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 97 20 2a b4 f0 23 01 00 00 vcvtsi2sdq 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 2a 72 7f vcvtsi2sdq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 2a b2 00 04 00 00 vcvtsi2sdq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 2a 72 80 vcvtsi2sdq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 2a b2 f8 fb ff ff vcvtsi2sdq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 20 2a f0 vcvtsi2ss %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 10 2a f0 vcvtsi2ss %eax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 50 2a f0 vcvtsi2ss %eax,\{ru-sae\},%xmm29,%xmm30 @@ -877,12 +877,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 16 50 2a f5 vcvtsi2ss %r13d,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 30 2a f5 vcvtsi2ss %r13d,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 70 2a f5 vcvtsi2ss %r13d,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 2a 31 vcvtsi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 16 20 2a b4 f0 23 01 00 00 vcvtsi2ss 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 2a 72 7f vcvtsi2ss 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 2a b2 00 02 00 00 vcvtsi2ss 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 2a 72 80 vcvtsi2ss -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 2a b2 fc fd ff ff vcvtsi2ss -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 2a 31 vcvtsi2ssl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 16 20 2a b4 f0 23 01 00 00 vcvtsi2ssl 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 2a 72 7f vcvtsi2ssl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 2a b2 00 02 00 00 vcvtsi2ssl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 2a 72 80 vcvtsi2ssl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 2a b2 fc fd ff ff vcvtsi2ssl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 20 2a f0 vcvtsi2ss %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 10 2a f0 vcvtsi2ss %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 50 2a f0 vcvtsi2ss %rax,\{ru-sae\},%xmm29,%xmm30 @@ -893,12 +893,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 96 50 2a f0 vcvtsi2ss %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 30 2a f0 vcvtsi2ss %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 70 2a f0 vcvtsi2ss %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 2a 31 vcvtsi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 96 20 2a b4 f0 23 01 00 00 vcvtsi2ss 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 2a 72 7f vcvtsi2ss 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 2a b2 00 04 00 00 vcvtsi2ss 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 2a 72 80 vcvtsi2ss -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 2a b2 f8 fb ff ff vcvtsi2ss -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 2a 31 vcvtsi2ssq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 96 20 2a b4 f0 23 01 00 00 vcvtsi2ssq 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 2a 72 7f vcvtsi2ssq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 2a b2 00 04 00 00 vcvtsi2ssq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 2a 72 80 vcvtsi2ssq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 2a b2 f8 fb ff ff vcvtsi2ssq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 01 16 27 5a f4 vcvtss2sd %xmm28,%xmm29,%xmm30\{%k7\} [ ]*[a-f0-9]+: 62 01 16 a7 5a f4 vcvtss2sd %xmm28,%xmm29,%xmm30\{%k7\}\{z\} [ ]*[a-f0-9]+: 62 01 16 17 5a f4 vcvtss2sd \{sae\},%xmm28,%xmm29,%xmm30\{%k7\} @@ -1625,12 +1625,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 61 17 20 7b f0 vcvtusi2sd %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 17 20 7b f5 vcvtusi2sd %ebp,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 17 20 7b f5 vcvtusi2sd %r13d,%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 7b 31 vcvtusi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 17 20 7b b4 f0 23 01 00 00 vcvtusi2sd 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 7b 72 7f vcvtusi2sd 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 7b b2 00 02 00 00 vcvtusi2sd 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 7b 72 80 vcvtusi2sd -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 7b b2 fc fd ff ff vcvtusi2sd -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 7b 31 vcvtusi2sdl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 17 20 7b b4 f0 23 01 00 00 vcvtusi2sdl 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 7b 72 7f vcvtusi2sdl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 7b b2 00 02 00 00 vcvtusi2sdl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 7b 72 80 vcvtusi2sdl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 7b b2 fc fd ff ff vcvtusi2sdl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 20 7b f0 vcvtusi2sd %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 10 7b f0 vcvtusi2sd %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 50 7b f0 vcvtusi2sd %rax,\{ru-sae\},%xmm29,%xmm30 @@ -1641,12 +1641,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 97 50 7b f0 vcvtusi2sd %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 30 7b f0 vcvtusi2sd %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 70 7b f0 vcvtusi2sd %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 7b 31 vcvtusi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 97 20 7b b4 f0 23 01 00 00 vcvtusi2sd 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 7b 72 7f vcvtusi2sd 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 7b b2 00 04 00 00 vcvtusi2sd 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 7b 72 80 vcvtusi2sd -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 7b b2 f8 fb ff ff vcvtusi2sd -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 7b 31 vcvtusi2sdq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 97 20 7b b4 f0 23 01 00 00 vcvtusi2sdq 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 7b 72 7f vcvtusi2sdq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 7b b2 00 04 00 00 vcvtusi2sdq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 7b 72 80 vcvtusi2sdq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 7b b2 f8 fb ff ff vcvtusi2sdq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 20 7b f0 vcvtusi2ss %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 10 7b f0 vcvtusi2ss %eax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 50 7b f0 vcvtusi2ss %eax,\{ru-sae\},%xmm29,%xmm30 @@ -1662,12 +1662,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 16 50 7b f5 vcvtusi2ss %r13d,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 30 7b f5 vcvtusi2ss %r13d,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 70 7b f5 vcvtusi2ss %r13d,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 7b 31 vcvtusi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 16 20 7b b4 f0 23 01 00 00 vcvtusi2ss 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 7b 72 7f vcvtusi2ss 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 7b b2 00 02 00 00 vcvtusi2ss 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 7b 72 80 vcvtusi2ss -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 7b b2 fc fd ff ff vcvtusi2ss -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 7b 31 vcvtusi2ssl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 16 20 7b b4 f0 23 01 00 00 vcvtusi2ssl 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 7b 72 7f vcvtusi2ssl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 7b b2 00 02 00 00 vcvtusi2ssl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 7b 72 80 vcvtusi2ssl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 7b b2 fc fd ff ff vcvtusi2ssl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 20 7b f0 vcvtusi2ss %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 10 7b f0 vcvtusi2ss %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 50 7b f0 vcvtusi2ss %rax,\{ru-sae\},%xmm29,%xmm30 @@ -1678,12 +1678,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 96 50 7b f0 vcvtusi2ss %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 30 7b f0 vcvtusi2ss %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 70 7b f0 vcvtusi2ss %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 7b 31 vcvtusi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 96 20 7b b4 f0 23 01 00 00 vcvtusi2ss 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 7b 72 7f vcvtusi2ss 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 7b b2 00 04 00 00 vcvtusi2ss 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 7b 72 80 vcvtusi2ss -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 7b b2 f8 fb ff ff vcvtusi2ss -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 7b 31 vcvtusi2ssq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 96 20 7b b4 f0 23 01 00 00 vcvtusi2ssq 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 7b 72 7f vcvtusi2ssq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 7b b2 00 04 00 00 vcvtusi2ssq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 7b 72 80 vcvtusi2ssq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 7b b2 f8 fb ff ff vcvtusi2ssq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 02 95 27 2d f4 vscalefsd %xmm28,%xmm29,%xmm30\{%k7\} [ ]*[a-f0-9]+: 62 02 95 a7 2d f4 vscalefsd %xmm28,%xmm29,%xmm30\{%k7\}\{z\} [ ]*[a-f0-9]+: 62 02 95 17 2d f4 vscalefsd \{rn-sae\},%xmm28,%xmm29,%xmm30\{%k7\} @@ -2583,12 +2583,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 61 17 20 2a f0 vcvtsi2sd %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 17 20 2a f5 vcvtsi2sd %ebp,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 17 20 2a f5 vcvtsi2sd %r13d,%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 2a 31 vcvtsi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 17 20 2a b4 f0 34 12 00 00 vcvtsi2sd 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 2a 72 7f vcvtsi2sd 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 2a b2 00 02 00 00 vcvtsi2sd 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 2a 72 80 vcvtsi2sd -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 2a b2 fc fd ff ff vcvtsi2sd -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 2a 31 vcvtsi2sdl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 17 20 2a b4 f0 34 12 00 00 vcvtsi2sdl 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 2a 72 7f vcvtsi2sdl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 2a b2 00 02 00 00 vcvtsi2sdl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 2a 72 80 vcvtsi2sdl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 2a b2 fc fd ff ff vcvtsi2sdl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 20 2a f0 vcvtsi2sd %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 10 2a f0 vcvtsi2sd %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 50 2a f0 vcvtsi2sd %rax,\{ru-sae\},%xmm29,%xmm30 @@ -2599,12 +2599,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 97 50 2a f0 vcvtsi2sd %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 30 2a f0 vcvtsi2sd %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 70 2a f0 vcvtsi2sd %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 2a 31 vcvtsi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 97 20 2a b4 f0 34 12 00 00 vcvtsi2sd 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 2a 72 7f vcvtsi2sd 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 2a b2 00 04 00 00 vcvtsi2sd 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 2a 72 80 vcvtsi2sd -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 2a b2 f8 fb ff ff vcvtsi2sd -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 2a 31 vcvtsi2sdq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 97 20 2a b4 f0 34 12 00 00 vcvtsi2sdq 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 2a 72 7f vcvtsi2sdq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 2a b2 00 04 00 00 vcvtsi2sdq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 2a 72 80 vcvtsi2sdq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 2a b2 f8 fb ff ff vcvtsi2sdq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 20 2a f0 vcvtsi2ss %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 10 2a f0 vcvtsi2ss %eax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 50 2a f0 vcvtsi2ss %eax,\{ru-sae\},%xmm29,%xmm30 @@ -2620,12 +2620,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 16 50 2a f5 vcvtsi2ss %r13d,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 30 2a f5 vcvtsi2ss %r13d,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 70 2a f5 vcvtsi2ss %r13d,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 2a 31 vcvtsi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 16 20 2a b4 f0 34 12 00 00 vcvtsi2ss 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 2a 72 7f vcvtsi2ss 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 2a b2 00 02 00 00 vcvtsi2ss 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 2a 72 80 vcvtsi2ss -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 2a b2 fc fd ff ff vcvtsi2ss -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 2a 31 vcvtsi2ssl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 16 20 2a b4 f0 34 12 00 00 vcvtsi2ssl 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 2a 72 7f vcvtsi2ssl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 2a b2 00 02 00 00 vcvtsi2ssl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 2a 72 80 vcvtsi2ssl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 2a b2 fc fd ff ff vcvtsi2ssl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 20 2a f0 vcvtsi2ss %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 10 2a f0 vcvtsi2ss %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 50 2a f0 vcvtsi2ss %rax,\{ru-sae\},%xmm29,%xmm30 @@ -2636,12 +2636,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 96 50 2a f0 vcvtsi2ss %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 30 2a f0 vcvtsi2ss %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 70 2a f0 vcvtsi2ss %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 2a 31 vcvtsi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 96 20 2a b4 f0 34 12 00 00 vcvtsi2ss 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 2a 72 7f vcvtsi2ss 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 2a b2 00 04 00 00 vcvtsi2ss 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 2a 72 80 vcvtsi2ss -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 2a b2 f8 fb ff ff vcvtsi2ss -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 2a 31 vcvtsi2ssq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 96 20 2a b4 f0 34 12 00 00 vcvtsi2ssq 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 2a 72 7f vcvtsi2ssq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 2a b2 00 04 00 00 vcvtsi2ssq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 2a 72 80 vcvtsi2ssq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 2a b2 f8 fb ff ff vcvtsi2ssq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 01 16 27 5a f4 vcvtss2sd %xmm28,%xmm29,%xmm30\{%k7\} [ ]*[a-f0-9]+: 62 01 16 a7 5a f4 vcvtss2sd %xmm28,%xmm29,%xmm30\{%k7\}\{z\} [ ]*[a-f0-9]+: 62 01 16 17 5a f4 vcvtss2sd \{sae\},%xmm28,%xmm29,%xmm30\{%k7\} @@ -3368,12 +3368,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 61 17 20 7b f0 vcvtusi2sd %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 17 20 7b f5 vcvtusi2sd %ebp,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 17 20 7b f5 vcvtusi2sd %r13d,%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 7b 31 vcvtusi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 17 20 7b b4 f0 34 12 00 00 vcvtusi2sd 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 7b 72 7f vcvtusi2sd 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 7b b2 00 02 00 00 vcvtusi2sd 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 7b 72 80 vcvtusi2sd -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 20 7b b2 fc fd ff ff vcvtusi2sd -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 7b 31 vcvtusi2sdl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 17 20 7b b4 f0 34 12 00 00 vcvtusi2sdl 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 7b 72 7f vcvtusi2sdl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 7b b2 00 02 00 00 vcvtusi2sdl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 7b 72 80 vcvtusi2sdl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 20 7b b2 fc fd ff ff vcvtusi2sdl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 20 7b f0 vcvtusi2sd %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 10 7b f0 vcvtusi2sd %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 50 7b f0 vcvtusi2sd %rax,\{ru-sae\},%xmm29,%xmm30 @@ -3384,12 +3384,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 97 50 7b f0 vcvtusi2sd %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 30 7b f0 vcvtusi2sd %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 70 7b f0 vcvtusi2sd %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 7b 31 vcvtusi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 97 20 7b b4 f0 34 12 00 00 vcvtusi2sd 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 7b 72 7f vcvtusi2sd 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 7b b2 00 04 00 00 vcvtusi2sd 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 7b 72 80 vcvtusi2sd -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 20 7b b2 f8 fb ff ff vcvtusi2sd -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 7b 31 vcvtusi2sdq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 97 20 7b b4 f0 34 12 00 00 vcvtusi2sdq 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 7b 72 7f vcvtusi2sdq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 7b b2 00 04 00 00 vcvtusi2sdq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 7b 72 80 vcvtusi2sdq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 20 7b b2 f8 fb ff ff vcvtusi2sdq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 20 7b f0 vcvtusi2ss %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 10 7b f0 vcvtusi2ss %eax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 50 7b f0 vcvtusi2ss %eax,\{ru-sae\},%xmm29,%xmm30 @@ -3405,12 +3405,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 16 50 7b f5 vcvtusi2ss %r13d,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 30 7b f5 vcvtusi2ss %r13d,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 70 7b f5 vcvtusi2ss %r13d,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 7b 31 vcvtusi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 16 20 7b b4 f0 34 12 00 00 vcvtusi2ss 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 7b 72 7f vcvtusi2ss 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 7b b2 00 02 00 00 vcvtusi2ss 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 7b 72 80 vcvtusi2ss -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 20 7b b2 fc fd ff ff vcvtusi2ss -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 7b 31 vcvtusi2ssl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 16 20 7b b4 f0 34 12 00 00 vcvtusi2ssl 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 7b 72 7f vcvtusi2ssl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 7b b2 00 02 00 00 vcvtusi2ssl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 7b 72 80 vcvtusi2ssl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 20 7b b2 fc fd ff ff vcvtusi2ssl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 20 7b f0 vcvtusi2ss %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 10 7b f0 vcvtusi2ss %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 50 7b f0 vcvtusi2ss %rax,\{ru-sae\},%xmm29,%xmm30 @@ -3421,12 +3421,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 96 50 7b f0 vcvtusi2ss %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 30 7b f0 vcvtusi2ss %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 70 7b f0 vcvtusi2ss %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 7b 31 vcvtusi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 96 20 7b b4 f0 34 12 00 00 vcvtusi2ss 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 7b 72 7f vcvtusi2ss 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 7b b2 00 04 00 00 vcvtusi2ss 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 7b 72 80 vcvtusi2ss -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 20 7b b2 f8 fb ff ff vcvtusi2ss -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 7b 31 vcvtusi2ssq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 96 20 7b b4 f0 34 12 00 00 vcvtusi2ssq 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 7b 72 7f vcvtusi2ssq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 7b b2 00 04 00 00 vcvtusi2ssq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 7b 72 80 vcvtusi2ssq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 20 7b b2 f8 fb ff ff vcvtusi2ssq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 02 95 27 2d f4 vscalefsd %xmm28,%xmm29,%xmm30\{%k7\} [ ]*[a-f0-9]+: 62 02 95 a7 2d f4 vscalefsd %xmm28,%xmm29,%xmm30\{%k7\}\{z\} [ ]*[a-f0-9]+: 62 02 95 17 2d f4 vscalefsd \{rn-sae\},%xmm28,%xmm29,%xmm30\{%k7\} diff --git a/gas/testsuite/gas/i386/x86-64-evex-lig512.d b/gas/testsuite/gas/i386/x86-64-evex-lig512.d index 22de4cbf531..83bd75a16eb 100644 --- a/gas/testsuite/gas/i386/x86-64-evex-lig512.d +++ b/gas/testsuite/gas/i386/x86-64-evex-lig512.d @@ -840,12 +840,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 61 17 40 2a f0 vcvtsi2sd %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 17 40 2a f5 vcvtsi2sd %ebp,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 17 40 2a f5 vcvtsi2sd %r13d,%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 2a 31 vcvtsi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 17 40 2a b4 f0 23 01 00 00 vcvtsi2sd 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 2a 72 7f vcvtsi2sd 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 2a b2 00 02 00 00 vcvtsi2sd 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 2a 72 80 vcvtsi2sd -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 2a b2 fc fd ff ff vcvtsi2sd -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 2a 31 vcvtsi2sdl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 17 40 2a b4 f0 23 01 00 00 vcvtsi2sdl 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 2a 72 7f vcvtsi2sdl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 2a b2 00 02 00 00 vcvtsi2sdl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 2a 72 80 vcvtsi2sdl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 2a b2 fc fd ff ff vcvtsi2sdl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 40 2a f0 vcvtsi2sd %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 10 2a f0 vcvtsi2sd %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 50 2a f0 vcvtsi2sd %rax,\{ru-sae\},%xmm29,%xmm30 @@ -856,12 +856,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 97 50 2a f0 vcvtsi2sd %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 30 2a f0 vcvtsi2sd %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 70 2a f0 vcvtsi2sd %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 2a 31 vcvtsi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 97 40 2a b4 f0 23 01 00 00 vcvtsi2sd 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 2a 72 7f vcvtsi2sd 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 2a b2 00 04 00 00 vcvtsi2sd 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 2a 72 80 vcvtsi2sd -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 2a b2 f8 fb ff ff vcvtsi2sd -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 2a 31 vcvtsi2sdq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 97 40 2a b4 f0 23 01 00 00 vcvtsi2sdq 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 2a 72 7f vcvtsi2sdq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 2a b2 00 04 00 00 vcvtsi2sdq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 2a 72 80 vcvtsi2sdq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 2a b2 f8 fb ff ff vcvtsi2sdq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 40 2a f0 vcvtsi2ss %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 10 2a f0 vcvtsi2ss %eax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 50 2a f0 vcvtsi2ss %eax,\{ru-sae\},%xmm29,%xmm30 @@ -877,12 +877,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 16 50 2a f5 vcvtsi2ss %r13d,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 30 2a f5 vcvtsi2ss %r13d,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 70 2a f5 vcvtsi2ss %r13d,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 2a 31 vcvtsi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 16 40 2a b4 f0 23 01 00 00 vcvtsi2ss 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 2a 72 7f vcvtsi2ss 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 2a b2 00 02 00 00 vcvtsi2ss 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 2a 72 80 vcvtsi2ss -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 2a b2 fc fd ff ff vcvtsi2ss -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 2a 31 vcvtsi2ssl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 16 40 2a b4 f0 23 01 00 00 vcvtsi2ssl 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 2a 72 7f vcvtsi2ssl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 2a b2 00 02 00 00 vcvtsi2ssl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 2a 72 80 vcvtsi2ssl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 2a b2 fc fd ff ff vcvtsi2ssl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 40 2a f0 vcvtsi2ss %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 10 2a f0 vcvtsi2ss %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 50 2a f0 vcvtsi2ss %rax,\{ru-sae\},%xmm29,%xmm30 @@ -893,12 +893,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 96 50 2a f0 vcvtsi2ss %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 30 2a f0 vcvtsi2ss %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 70 2a f0 vcvtsi2ss %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 2a 31 vcvtsi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 96 40 2a b4 f0 23 01 00 00 vcvtsi2ss 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 2a 72 7f vcvtsi2ss 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 2a b2 00 04 00 00 vcvtsi2ss 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 2a 72 80 vcvtsi2ss -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 2a b2 f8 fb ff ff vcvtsi2ss -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 2a 31 vcvtsi2ssq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 96 40 2a b4 f0 23 01 00 00 vcvtsi2ssq 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 2a 72 7f vcvtsi2ssq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 2a b2 00 04 00 00 vcvtsi2ssq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 2a 72 80 vcvtsi2ssq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 2a b2 f8 fb ff ff vcvtsi2ssq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 01 16 47 5a f4 vcvtss2sd %xmm28,%xmm29,%xmm30\{%k7\} [ ]*[a-f0-9]+: 62 01 16 c7 5a f4 vcvtss2sd %xmm28,%xmm29,%xmm30\{%k7\}\{z\} [ ]*[a-f0-9]+: 62 01 16 17 5a f4 vcvtss2sd \{sae\},%xmm28,%xmm29,%xmm30\{%k7\} @@ -1625,12 +1625,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 61 17 40 7b f0 vcvtusi2sd %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 17 40 7b f5 vcvtusi2sd %ebp,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 17 40 7b f5 vcvtusi2sd %r13d,%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 7b 31 vcvtusi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 17 40 7b b4 f0 23 01 00 00 vcvtusi2sd 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 7b 72 7f vcvtusi2sd 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 7b b2 00 02 00 00 vcvtusi2sd 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 7b 72 80 vcvtusi2sd -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 7b b2 fc fd ff ff vcvtusi2sd -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 7b 31 vcvtusi2sdl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 17 40 7b b4 f0 23 01 00 00 vcvtusi2sdl 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 7b 72 7f vcvtusi2sdl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 7b b2 00 02 00 00 vcvtusi2sdl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 7b 72 80 vcvtusi2sdl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 7b b2 fc fd ff ff vcvtusi2sdl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 40 7b f0 vcvtusi2sd %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 10 7b f0 vcvtusi2sd %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 50 7b f0 vcvtusi2sd %rax,\{ru-sae\},%xmm29,%xmm30 @@ -1641,12 +1641,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 97 50 7b f0 vcvtusi2sd %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 30 7b f0 vcvtusi2sd %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 70 7b f0 vcvtusi2sd %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 7b 31 vcvtusi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 97 40 7b b4 f0 23 01 00 00 vcvtusi2sd 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 7b 72 7f vcvtusi2sd 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 7b b2 00 04 00 00 vcvtusi2sd 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 7b 72 80 vcvtusi2sd -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 7b b2 f8 fb ff ff vcvtusi2sd -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 7b 31 vcvtusi2sdq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 97 40 7b b4 f0 23 01 00 00 vcvtusi2sdq 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 7b 72 7f vcvtusi2sdq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 7b b2 00 04 00 00 vcvtusi2sdq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 7b 72 80 vcvtusi2sdq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 7b b2 f8 fb ff ff vcvtusi2sdq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 40 7b f0 vcvtusi2ss %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 10 7b f0 vcvtusi2ss %eax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 50 7b f0 vcvtusi2ss %eax,\{ru-sae\},%xmm29,%xmm30 @@ -1662,12 +1662,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 16 50 7b f5 vcvtusi2ss %r13d,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 30 7b f5 vcvtusi2ss %r13d,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 70 7b f5 vcvtusi2ss %r13d,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 7b 31 vcvtusi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 16 40 7b b4 f0 23 01 00 00 vcvtusi2ss 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 7b 72 7f vcvtusi2ss 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 7b b2 00 02 00 00 vcvtusi2ss 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 7b 72 80 vcvtusi2ss -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 7b b2 fc fd ff ff vcvtusi2ss -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 7b 31 vcvtusi2ssl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 16 40 7b b4 f0 23 01 00 00 vcvtusi2ssl 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 7b 72 7f vcvtusi2ssl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 7b b2 00 02 00 00 vcvtusi2ssl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 7b 72 80 vcvtusi2ssl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 7b b2 fc fd ff ff vcvtusi2ssl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 40 7b f0 vcvtusi2ss %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 10 7b f0 vcvtusi2ss %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 50 7b f0 vcvtusi2ss %rax,\{ru-sae\},%xmm29,%xmm30 @@ -1678,12 +1678,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 96 50 7b f0 vcvtusi2ss %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 30 7b f0 vcvtusi2ss %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 70 7b f0 vcvtusi2ss %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 7b 31 vcvtusi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 96 40 7b b4 f0 23 01 00 00 vcvtusi2ss 0x123\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 7b 72 7f vcvtusi2ss 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 7b b2 00 04 00 00 vcvtusi2ss 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 7b 72 80 vcvtusi2ss -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 7b b2 f8 fb ff ff vcvtusi2ss -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 7b 31 vcvtusi2ssq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 96 40 7b b4 f0 23 01 00 00 vcvtusi2ssq 0x123\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 7b 72 7f vcvtusi2ssq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 7b b2 00 04 00 00 vcvtusi2ssq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 7b 72 80 vcvtusi2ssq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 7b b2 f8 fb ff ff vcvtusi2ssq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 02 95 47 2d f4 vscalefsd %xmm28,%xmm29,%xmm30\{%k7\} [ ]*[a-f0-9]+: 62 02 95 c7 2d f4 vscalefsd %xmm28,%xmm29,%xmm30\{%k7\}\{z\} [ ]*[a-f0-9]+: 62 02 95 17 2d f4 vscalefsd \{rn-sae\},%xmm28,%xmm29,%xmm30\{%k7\} @@ -2583,12 +2583,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 61 17 40 2a f0 vcvtsi2sd %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 17 40 2a f5 vcvtsi2sd %ebp,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 17 40 2a f5 vcvtsi2sd %r13d,%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 2a 31 vcvtsi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 17 40 2a b4 f0 34 12 00 00 vcvtsi2sd 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 2a 72 7f vcvtsi2sd 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 2a b2 00 02 00 00 vcvtsi2sd 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 2a 72 80 vcvtsi2sd -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 2a b2 fc fd ff ff vcvtsi2sd -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 2a 31 vcvtsi2sdl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 17 40 2a b4 f0 34 12 00 00 vcvtsi2sdl 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 2a 72 7f vcvtsi2sdl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 2a b2 00 02 00 00 vcvtsi2sdl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 2a 72 80 vcvtsi2sdl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 2a b2 fc fd ff ff vcvtsi2sdl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 40 2a f0 vcvtsi2sd %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 10 2a f0 vcvtsi2sd %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 50 2a f0 vcvtsi2sd %rax,\{ru-sae\},%xmm29,%xmm30 @@ -2599,12 +2599,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 97 50 2a f0 vcvtsi2sd %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 30 2a f0 vcvtsi2sd %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 70 2a f0 vcvtsi2sd %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 2a 31 vcvtsi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 97 40 2a b4 f0 34 12 00 00 vcvtsi2sd 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 2a 72 7f vcvtsi2sd 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 2a b2 00 04 00 00 vcvtsi2sd 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 2a 72 80 vcvtsi2sd -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 2a b2 f8 fb ff ff vcvtsi2sd -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 2a 31 vcvtsi2sdq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 97 40 2a b4 f0 34 12 00 00 vcvtsi2sdq 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 2a 72 7f vcvtsi2sdq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 2a b2 00 04 00 00 vcvtsi2sdq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 2a 72 80 vcvtsi2sdq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 2a b2 f8 fb ff ff vcvtsi2sdq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 40 2a f0 vcvtsi2ss %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 10 2a f0 vcvtsi2ss %eax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 50 2a f0 vcvtsi2ss %eax,\{ru-sae\},%xmm29,%xmm30 @@ -2620,12 +2620,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 16 50 2a f5 vcvtsi2ss %r13d,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 30 2a f5 vcvtsi2ss %r13d,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 70 2a f5 vcvtsi2ss %r13d,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 2a 31 vcvtsi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 16 40 2a b4 f0 34 12 00 00 vcvtsi2ss 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 2a 72 7f vcvtsi2ss 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 2a b2 00 02 00 00 vcvtsi2ss 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 2a 72 80 vcvtsi2ss -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 2a b2 fc fd ff ff vcvtsi2ss -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 2a 31 vcvtsi2ssl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 16 40 2a b4 f0 34 12 00 00 vcvtsi2ssl 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 2a 72 7f vcvtsi2ssl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 2a b2 00 02 00 00 vcvtsi2ssl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 2a 72 80 vcvtsi2ssl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 2a b2 fc fd ff ff vcvtsi2ssl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 40 2a f0 vcvtsi2ss %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 10 2a f0 vcvtsi2ss %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 50 2a f0 vcvtsi2ss %rax,\{ru-sae\},%xmm29,%xmm30 @@ -2636,12 +2636,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 96 50 2a f0 vcvtsi2ss %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 30 2a f0 vcvtsi2ss %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 70 2a f0 vcvtsi2ss %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 2a 31 vcvtsi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 96 40 2a b4 f0 34 12 00 00 vcvtsi2ss 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 2a 72 7f vcvtsi2ss 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 2a b2 00 04 00 00 vcvtsi2ss 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 2a 72 80 vcvtsi2ss -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 2a b2 f8 fb ff ff vcvtsi2ss -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 2a 31 vcvtsi2ssq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 96 40 2a b4 f0 34 12 00 00 vcvtsi2ssq 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 2a 72 7f vcvtsi2ssq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 2a b2 00 04 00 00 vcvtsi2ssq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 2a 72 80 vcvtsi2ssq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 2a b2 f8 fb ff ff vcvtsi2ssq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 01 16 47 5a f4 vcvtss2sd %xmm28,%xmm29,%xmm30\{%k7\} [ ]*[a-f0-9]+: 62 01 16 c7 5a f4 vcvtss2sd %xmm28,%xmm29,%xmm30\{%k7\}\{z\} [ ]*[a-f0-9]+: 62 01 16 17 5a f4 vcvtss2sd \{sae\},%xmm28,%xmm29,%xmm30\{%k7\} @@ -3368,12 +3368,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 61 17 40 7b f0 vcvtusi2sd %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 17 40 7b f5 vcvtusi2sd %ebp,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 17 40 7b f5 vcvtusi2sd %r13d,%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 7b 31 vcvtusi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 17 40 7b b4 f0 34 12 00 00 vcvtusi2sd 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 7b 72 7f vcvtusi2sd 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 7b b2 00 02 00 00 vcvtusi2sd 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 7b 72 80 vcvtusi2sd -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 17 40 7b b2 fc fd ff ff vcvtusi2sd -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 7b 31 vcvtusi2sdl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 17 40 7b b4 f0 34 12 00 00 vcvtusi2sdl 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 7b 72 7f vcvtusi2sdl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 7b b2 00 02 00 00 vcvtusi2sdl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 7b 72 80 vcvtusi2sdl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 17 40 7b b2 fc fd ff ff vcvtusi2sdl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 40 7b f0 vcvtusi2sd %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 10 7b f0 vcvtusi2sd %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 97 50 7b f0 vcvtusi2sd %rax,\{ru-sae\},%xmm29,%xmm30 @@ -3384,12 +3384,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 97 50 7b f0 vcvtusi2sd %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 30 7b f0 vcvtusi2sd %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 97 70 7b f0 vcvtusi2sd %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 7b 31 vcvtusi2sd \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 97 40 7b b4 f0 34 12 00 00 vcvtusi2sd 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 7b 72 7f vcvtusi2sd 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 7b b2 00 04 00 00 vcvtusi2sd 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 7b 72 80 vcvtusi2sd -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 97 40 7b b2 f8 fb ff ff vcvtusi2sd -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 7b 31 vcvtusi2sdq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 97 40 7b b4 f0 34 12 00 00 vcvtusi2sdq 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 7b 72 7f vcvtusi2sdq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 7b b2 00 04 00 00 vcvtusi2sdq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 7b 72 80 vcvtusi2sdq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 97 40 7b b2 f8 fb ff ff vcvtusi2sdq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 40 7b f0 vcvtusi2ss %eax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 10 7b f0 vcvtusi2ss %eax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 16 50 7b f0 vcvtusi2ss %eax,\{ru-sae\},%xmm29,%xmm30 @@ -3405,12 +3405,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 16 50 7b f5 vcvtusi2ss %r13d,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 30 7b f5 vcvtusi2ss %r13d,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 16 70 7b f5 vcvtusi2ss %r13d,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 7b 31 vcvtusi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 16 40 7b b4 f0 34 12 00 00 vcvtusi2ss 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 7b 72 7f vcvtusi2ss 0x1fc\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 7b b2 00 02 00 00 vcvtusi2ss 0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 7b 72 80 vcvtusi2ss -0x200\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 16 40 7b b2 fc fd ff ff vcvtusi2ss -0x204\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 7b 31 vcvtusi2ssl \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 16 40 7b b4 f0 34 12 00 00 vcvtusi2ssl 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 7b 72 7f vcvtusi2ssl 0x1fc\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 7b b2 00 02 00 00 vcvtusi2ssl 0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 7b 72 80 vcvtusi2ssl -0x200\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 16 40 7b b2 fc fd ff ff vcvtusi2ssl -0x204\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 40 7b f0 vcvtusi2ss %rax,%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 10 7b f0 vcvtusi2ss %rax,\{rn-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 61 96 50 7b f0 vcvtusi2ss %rax,\{ru-sae\},%xmm29,%xmm30 @@ -3421,12 +3421,12 @@ Disassembly of section .text: [ ]*[a-f0-9]+: 62 41 96 50 7b f0 vcvtusi2ss %r8,\{ru-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 30 7b f0 vcvtusi2ss %r8,\{rd-sae\},%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 41 96 70 7b f0 vcvtusi2ss %r8,\{rz-sae\},%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 7b 31 vcvtusi2ss \(%rcx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 21 96 40 7b b4 f0 34 12 00 00 vcvtusi2ss 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 7b 72 7f vcvtusi2ss 0x3f8\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 7b b2 00 04 00 00 vcvtusi2ss 0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 7b 72 80 vcvtusi2ss -0x400\(%rdx\),%xmm29,%xmm30 -[ ]*[a-f0-9]+: 62 61 96 40 7b b2 f8 fb ff ff vcvtusi2ss -0x408\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 7b 31 vcvtusi2ssq \(%rcx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 21 96 40 7b b4 f0 34 12 00 00 vcvtusi2ssq 0x1234\(%rax,%r14,8\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 7b 72 7f vcvtusi2ssq 0x3f8\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 7b b2 00 04 00 00 vcvtusi2ssq 0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 7b 72 80 vcvtusi2ssq -0x400\(%rdx\),%xmm29,%xmm30 +[ ]*[a-f0-9]+: 62 61 96 40 7b b2 f8 fb ff ff vcvtusi2ssq -0x408\(%rdx\),%xmm29,%xmm30 [ ]*[a-f0-9]+: 62 02 95 47 2d f4 vscalefsd %xmm28,%xmm29,%xmm30\{%k7\} [ ]*[a-f0-9]+: 62 02 95 c7 2d f4 vscalefsd %xmm28,%xmm29,%xmm30\{%k7\}\{z\} [ ]*[a-f0-9]+: 62 02 95 17 2d f4 vscalefsd \{rn-sae\},%xmm28,%xmm29,%xmm30\{%k7\} diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index d99b85cf776..acd044b1701 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2018-07-24 Jan Beulich + + * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd, + vcvtusi2ss, and vcvtusi2sd. + * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss): + Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms. + * i386-tbl.h: Re-generate. + 2018-07-23 Claudiu Zissulescu * arc-opc.c (extract_w6): Fix extending the sign. diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index c2278001d0d..8b825789340 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -3045,13 +3045,13 @@ static const struct dis386 evex_table[][256] = { }, /* EVEX_W_0F2A_P_1 */ { - { "vcvtsi2ss", { XMScalar, VexScalar, EXxEVexR, Ed }, 0 }, - { "vcvtsi2ss", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, + { "vcvtsi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Ed }, 0 }, + { "vcvtsi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, }, /* EVEX_W_0F2A_P_3 */ { - { "vcvtsi2sd", { XMScalar, VexScalar, Ed }, 0 }, - { "vcvtsi2sd", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, + { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ed }, 0 }, + { "vcvtsi2sd%LQ", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, }, /* EVEX_W_0F2B_P_0 */ { @@ -3382,8 +3382,8 @@ static const struct dis386 evex_table[][256] = { }, /* EVEX_W_0F7B_P_1 */ { - { "vcvtusi2ss", { XMScalar, VexScalar, EXxEVexR, Ed }, 0 }, - { "vcvtusi2ss", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, + { "vcvtusi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Ed }, 0 }, + { "vcvtusi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, }, /* EVEX_W_0F7B_P_2 */ { @@ -3392,8 +3392,8 @@ static const struct dis386 evex_table[][256] = { }, /* EVEX_W_0F7B_P_3 */ { - { "vcvtusi2sd", { XMScalar, VexScalar, Ed }, 0 }, - { "vcvtusi2sd", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, + { "vcvtusi2sd%LQ", { XMScalar, VexScalar, Ed }, 0 }, + { "vcvtusi2sd%LQ", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, }, /* EVEX_W_0F7E_P_1 */ { diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 3a669d7d448..d22f23c8c8f 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3455,21 +3455,21 @@ vcvtsd2usi, 3, 0xF279, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|IgnoreSize| vcvtsd2ss, 3, 0xF25A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtsd2ss, 4, 0xF25A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM } -vcvtsi2sd, 3, 0xF22A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2sd, 3, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sd, 3, 0xF22A, None, 1, CpuAVX512F|CpuNo64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2sd, 3, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtsi2sd, 4, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM } vcvtsi2sd, 4, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM } -vcvtusi2sd, 3, 0xF27B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2sd, 3, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sd, 3, 0xF27B, None, 1, CpuAVX512F|CpuNo64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2sd, 3, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtusi2sd, 4, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM } vcvtusi2sd, 4, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM } -vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F|CpuNo64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg32|Reg64, Imm8, RegXMM, RegXMM } vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg32|Reg64, RegXMM, RegXMM } -vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F|CpuNo64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg32|Reg64, Imm8, RegXMM, RegXMM } vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg32|Reg64, RegXMM, RegXMM } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 5be43472456..6a8f2298f23 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -34661,12 +34661,12 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, + 0, 0, 0, 1, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -34682,12 +34682,12 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 2, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, + 0, 1, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, @@ -34787,12 +34787,12 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, + 0, 0, 0, 1, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -34808,12 +34808,12 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 2, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, + 0, 1, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, @@ -63205,12 +63205,12 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, + 0, 0, 0, 1, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -63226,12 +63226,12 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 2, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, + 0, 1, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, @@ -63291,12 +63291,12 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, + 0, 0, 0, 1, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, + { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -63312,12 +63312,12 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 1, 2, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, + 0, 1, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,