From: lkcl <lkcl@web>
Date: Sun, 2 Apr 2023 21:55:50 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~171
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=417c467eb90a9647b6ea8de3881cc111cc8aa4f8;p=libreriscv.git

---

diff --git a/openpower/isa.mdwn b/openpower/isa.mdwn
index 978f9868b..df1797b0b 100644
--- a/openpower/isa.mdwn
+++ b/openpower/isa.mdwn
@@ -41,6 +41,11 @@ Explanation of the rules for twin register targets
 * [[isa/svfparith]]
 * [[isa/bitmanip]]
 
+Scalar "Post-Increment" Draft Load/Store with Update
+
+* [[isa/pifixedload]]
+* [[isa/pifixedstore]]
+
 Part of the DRAFT Simple-V Specification:
 
 * [[isa/simplev]]