From: Luke Kenneth Casson Leighton Date: Tue, 29 Dec 2020 14:18:07 +0000 (+0000) Subject: update sv_analysis X-Git-Tag: convert-csv-opcode-to-binary~732 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4185943a266cf81a6a8fd9512b87f90f4b41dfe7;p=libreriscv.git update sv_analysis --- diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv index 8d27dd75f..634d3fb0b 100644 --- a/openpower/isatables/RM-2P-1S1D.csv +++ b/openpower/isatables/RM-2P-1S1D.csv @@ -3,7 +3,7 @@ mcrf,2P,EXTRA3,d:BF,s:BFA,0,0,0,0,0,0,BFA,BF mfcr/mfocrf,2P,EXTRA3,d:RT,s:CR,0,0,0,0,0,RT,WHOLE_REG,0 setb,2P,EXTRA3,d:RT,s:BFA,0,0,0,0,0,RT,BFA,0 5/0=ftsqrt,2P,EXTRA3,d:BF,s:FRB,0,0,0,FRB,0,0,0,BF -22/7=mtfsf,2P,EXTRA3,TODO,0,0,0,0,FRB,0,0,0,CR1 +22/7=mtfsf,2P,EXTRA3,d:CR1,s:FRB,0,0,0,FRB,0,0,0,CR1 cmpli,2P,EXTRA3,d:BF,s:RA,0,0,RA,0,0,0,0,BF cmpi,2P,EXTRA3,d:BF,s:RA,0,0,RA,0,0,0,0,BF neg,2P,EXTRA3,d:RT,s:RA,0,0,RA,0,0,RT,0,0 diff --git a/openpower/sv_analysis.py b/openpower/sv_analysis.py index 62c83de9e..b354bb3fc 100644 --- a/openpower/sv_analysis.py +++ b/openpower/sv_analysis.py @@ -452,6 +452,9 @@ def process_csvs(): elif regs == ['','FRB','','FRT','0','CR1']: res['0'] = 'd:FRT,d:CR1' # FRT,CR1: Rdest1_EXTRA3 res['1'] = 's:FRA' # FRA: Rsrc1_EXTRA3 + elif regs == ['','FRB','','','','CR1']: + res['0'] = 'd:CR1' # CR1: Rdest1_EXTRA3 + res['1'] = 's:FRB' # FRA: Rsrc1_EXTRA3 elif regs == ['','FRB','','','','BF']: res['0'] = 'd:BF' # BF: Rdest1_EXTRA3 res['1'] = 's:FRB' # FRA: Rsrc1_EXTRA3