From: Paul Mackerras <paulus@ozlabs.org>
Date: Tue, 30 Jun 2020 05:01:06 +0000 (+1000)
Subject: Merge pull request #206 from Jbalkind/icachecleanup
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=419c9a68e81c94d3947e87256f7d28df2cf6bc06;p=microwatt.git

Merge pull request #206 from Jbalkind/icachecleanup

Icache constants cleanup
---

419c9a68e81c94d3947e87256f7d28df2cf6bc06
diff --cc icache.vhdl
index 739e047,357f74d..dab2505
--- a/icache.vhdl
+++ b/icache.vhdl
@@@ -115,10 -113,9 +116,10 @@@ architecture rtl of icache i
      subtype row_t is integer range 0 to BRAM_ROWS-1;
      subtype index_t is integer range 0 to NUM_LINES-1;
      subtype way_t is integer range 0 to NUM_WAYS-1;
 +    subtype row_in_line_t is unsigned(ROW_LINEBITS-1 downto 0);
  
      -- The cache data BRAM organized as described above for each way
-     subtype cache_row_t is std_ulogic_vector(wishbone_data_bits-1 downto 0);
+     subtype cache_row_t is std_ulogic_vector(ROW_SIZE_BITS-1 downto 0);
  
      -- The cache tags LUTRAM has a row per set. Vivado is a pain and will
      -- not handle a clean (commented) definition of the cache tags as a 3d