From: Richard Henderson Date: Tue, 21 Dec 2004 16:46:04 +0000 (-0800) Subject: i386.c (x86_sse_split_regs): Rename from x86_sse_partial_regs. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=41afe4ef3e66834becefe1d2ad5e879c878f1008;p=gcc.git i386.c (x86_sse_split_regs): Rename from x86_sse_partial_regs. * config/i386/i386.c (x86_sse_split_regs): Rename from x86_sse_partial_regs. * config/i386/i386.h (x86_sse_split_regs): Likewise. (TARGET_SSE_SPLIT_REGS): Rename from TARGET_SSE_PARTIAL_REGS. * config/i386/i386.md (*): Update to match. Remove two floatsisf splitters that use it. From-SVN: r92458 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7a7b649e999..f65773c70c0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,14 @@ 2004-12-21 Richard Henderson + * config/i386/i386.c (x86_sse_split_regs): Rename from + x86_sse_partial_regs. + * config/i386/i386.h (x86_sse_split_regs): Likewise. + (TARGET_SSE_SPLIT_REGS): Rename from TARGET_SSE_PARTIAL_REGS. + * config/i386/i386.md (*): Update to match. Remove two + floatsisf splitters that use it. + + * config/i386/i386.h (x86_sse_partial_regs_for_cvtsd2ss): Remove. + * config/i386/i386.c (x86_sse_partial_regs_for_cvtsd2ss): Remove. * config/i386/i386.h (TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS): Remove. * config/i386/i386.md (truncdfsf2_1_sse): Don't test it. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index ad46febf365..a6273cadd6b 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -562,10 +562,11 @@ const int x86_decompose_lea = m_PENT4 | m_NOCONA; const int x86_shift1 = ~m_486; const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA; const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO; -/* Set for machines where the type and dependencies are resolved on SSE register - parts instead of whole registers, so we may maintain just lower part of - scalar values in proper format leaving the upper part undefined. */ -const int x86_sse_partial_regs = m_ATHLON_K8; +/* Set for machines where the type and dependencies are resolved on SSE + register parts instead of whole registers, so we may maintain just + lower part of scalar values in proper format leaving the upper part + undefined. */ +const int x86_sse_split_regs = m_ATHLON_K8; const int x86_sse_typeless_stores = m_ATHLON_K8; const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA; const int x86_use_ffreep = m_ATHLON_K8; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 80fe6cdb029..383617214dd 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -243,9 +243,9 @@ extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; extern const int x86_accumulate_outgoing_args, x86_prologue_using_move; extern const int x86_epilogue_using_move, x86_decompose_lea; extern const int x86_arch_always_fancy_math_387, x86_shift1; -extern const int x86_sse_partial_reg_dependency, x86_sse_partial_regs; +extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs; extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor; -extern const int x86_use_ffreep, x86_sse_partial_regs_for_cvtsd2ss; +extern const int x86_use_ffreep; extern const int x86_inter_unit_moves, x86_schedule; extern const int x86_use_bt; extern int x86_prefetch_sse; @@ -286,7 +286,7 @@ extern int x86_prefetch_sse; #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK) #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ (x86_sse_partial_reg_dependency & TUNEMASK) -#define TARGET_SSE_PARTIAL_REGS (x86_sse_partial_regs & TUNEMASK) +#define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK) #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK) #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK) #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 3cdfc71517c..285df847f56 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -2268,7 +2268,7 @@ (if_then_else (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY") (const_int 0)) - (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS") + (ne (symbol_ref "TARGET_SSE_SPLIT_REGS") (const_int 0))) (const_string "V4SF") (const_string "SF")) @@ -2358,7 +2358,7 @@ (if_then_else (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY") (const_int 0)) - (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS") + (ne (symbol_ref "TARGET_SSE_SPLIT_REGS") (const_int 0))) (const_string "V4SF") (const_string "SF")) @@ -2554,7 +2554,7 @@ of register. */ (eq_attr "alternative" "7") (if_then_else - (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS") + (ne (symbol_ref "TARGET_SSE_SPLIT_REGS") (const_int 0)) (const_string "V1DF") (const_string "DF")) @@ -2674,7 +2674,7 @@ of register. */ (eq_attr "alternative" "7") (if_then_else - (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS") + (ne (symbol_ref "TARGET_SSE_SPLIT_REGS") (const_int 0)) (const_string "V1DF") (const_string "DF")) @@ -4480,23 +4480,6 @@ (set_attr "athlon_decode" "vector,double") (set_attr "fp_int_src" "true")]) -; Avoid possible reformatting penalty on the destination by first -; zeroing it out -(define_split - [(set (match_operand:SF 0 "register_operand" "") - (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] - "reload_completed - && TARGET_SSE_MATH && TARGET_SSE_PARTIAL_REGS - && SSE_REG_P (operands[0])" - [(const_int 0)] -{ - rtx dest; - dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0); - emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode))); - emit_insn (gen_cvtsi2ss (dest, dest, operands[1])); - DONE; -}) - (define_insn "*floatsisf2_i387" [(set (match_operand:SF 0 "register_operand" "=f,f") (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))] @@ -4538,23 +4521,6 @@ (set_attr "athlon_decode" "vector,double") (set_attr "fp_int_src" "true")]) -; Avoid possible reformatting penalty on the destination by first -; zeroing it out -(define_split - [(set (match_operand:SF 0 "register_operand" "") - (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))] - "reload_completed - && TARGET_64BIT && TARGET_SSE_MATH && TARGET_SSE_PARTIAL_REGS - && SSE_REG_P (operands[0])" - [(const_int 0)] -{ - rtx dest; - dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0); - emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode))); - emit_insn (gen_cvtsi2ssq (dest, dest, operands[1])); - DONE; -}) - (define_insn "*floatdisf2_i387" [(set (match_operand:SF 0 "register_operand" "=f,f") (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))] @@ -18266,8 +18232,7 @@ (set (match_dup 0) (ior:V2DF (match_dup 6) (match_dup 7)))] { - if (GET_MODE (operands[2]) == DFmode - && TARGET_SSE_PARTIAL_REGS && !optimize_size) + if (TARGET_SSE_SPLIT_REGS && !optimize_size) { rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0); emit_insn (gen_sse2_unpcklpd (op, op, op)); @@ -18429,8 +18394,7 @@ [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)])) (set (match_dup 8) (and:V2DF (match_dup 6) (match_dup 7)))] { - if (TARGET_SSE_PARTIAL_REGS && !optimize_size - && GET_MODE (operands[2]) == DFmode) + if (TARGET_SSE_SPLIT_REGS && !optimize_size) { if (REG_P (operands[2])) {