From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Tue, 25 Sep 2018 16:35:35 +0000 (+0100)
Subject: sim-se: Set ArmProcess64 hwcaps depending on ID regs
X-Git-Tag: v19.0.0.0~1697
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=41b339367c2c858c1dc9fb98931ceb6f3efb5b57;p=gem5.git

sim-se: Set ArmProcess64 hwcaps depending on ID regs

ArmProcess64 needs to query AArch64 ID registers to check which hw
capability is going to report in the appropriate aux vector's entry.

Change-Id: I1e1294b831e902226f9b162f25e841e53b940454
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13164
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
---

diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 0dfd393d6..095bd3e53 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -204,7 +204,49 @@ ArmProcess64::armHwcapImpl() const
         Arm_Flagm = 1 << 27
     };
 
-    return Arm_Fp | Arm_Asimd | Arm_Evtstrm | Arm_Crc32;
+    uint32_t hwcap = 0;
+
+    ThreadContext *tc = system->getThreadContext(contextIds[0]);
+
+    const AA64PFR0 pf_r0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1);
+
+    hwcap |= (pf_r0.fp == 0) ? Arm_Fp : 0;
+    hwcap |= (pf_r0.fp == 1) ? Arm_Fphp | Arm_Fp : 0;
+    hwcap |= (pf_r0.advsimd == 0) ? Arm_Asimd : 0;
+    hwcap |= (pf_r0.advsimd == 1) ? Arm_Asimdhp | Arm_Asimd : 0;
+    hwcap |= (pf_r0.sve >= 1) ? Arm_Sve : 0;
+    hwcap |= (pf_r0.dit >= 1) ? Arm_Dit : 0;
+
+    const AA64ISAR0 isa_r0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
+
+    hwcap |= (isa_r0.aes >= 1) ? Arm_Aes : 0;
+    hwcap |= (isa_r0.aes >= 2) ? Arm_Pmull : 0;
+    hwcap |= (isa_r0.sha1 >= 1) ? Arm_Sha1 : 0;
+    hwcap |= (isa_r0.sha2 >= 1) ? Arm_Sha2 : 0;
+    hwcap |= (isa_r0.sha2 >= 2) ? Arm_Sha512 : 0;
+    hwcap |= (isa_r0.crc32 >= 1) ? Arm_Crc32 : 0;
+    hwcap |= (isa_r0.atomic >= 1) ? Arm_Atomics : 0;
+    hwcap |= (isa_r0.rdm >= 1) ? Arm_Asimdrdm : 0;
+    hwcap |= (isa_r0.sha3 >= 1) ? Arm_Sha3 : 0;
+    hwcap |= (isa_r0.sm3 >= 1) ? Arm_Sm3 : 0;
+    hwcap |= (isa_r0.sm4 >= 1) ? Arm_Sm4 : 0;
+    hwcap |= (isa_r0.dp >= 1) ? Arm_Asimddp : 0;
+    hwcap |= (isa_r0.fhm >= 1) ? Arm_Asimdfhm : 0;
+    hwcap |= (isa_r0.ts >= 1) ? Arm_Flagm : 0;
+
+    const AA64ISAR1 isa_r1 = tc->readMiscReg(MISCREG_ID_AA64ISAR1_EL1);
+
+    hwcap |= (isa_r1.dpb >= 1) ? Arm_Dcpop : 0;
+    hwcap |= (isa_r1.jscvt >= 1) ? Arm_Jscvt : 0;
+    hwcap |= (isa_r1.fcma >= 1) ? Arm_Fcma : 0;
+    hwcap |= (isa_r1.lrcpc >= 1) ? Arm_Lrcpc : 0;
+    hwcap |= (isa_r1.lrcpc >= 2) ? Arm_Ilrcpc : 0;
+
+    const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
+
+    hwcap |= (mm_fr2.at >= 1) ? Arm_Uscat : 0;
+
+    return hwcap;
 }
 
 template <class IntType>