From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Sun, 8 May 2016 04:14:42 +0000 (-0700)
Subject: Fixed typo in port name
X-Git-Tag: yosys-0.7~226^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=41bbad4e4c25bc1b0227348ec0329187c8688c4b;p=yosys.git

Fixed typo in port name
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 5a59a06b4..b9cfbe665 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -286,7 +286,7 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 	
 	reg[15:0] shreg = 0;
 	
-	always @(posedge clk, negedge nRST) begin
+	always @(posedge CLK, negedge nRST) begin
 		
 		if(!nRST)
 			shreg = 0;