From: lkcl <lkcl@web>
Date: Tue, 3 Aug 2021 02:56:23 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~521
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=41d58e17f77725704a4fa69319f4ee2227b4f727;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index f21f329e0..dfa2ecda0 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -40,7 +40,8 @@ for non-ALL mode (Great Big Or) on first success early
 exit also occurs, however this time with the Branch proceeding.
 In both cases the testing of the Vector of CRs should be
 done in linear sequential order (or in REMAP re-sequenced order):
-such that tests beyond the exit point are *not* carried out.
+such that tests that are sequentially beyond the exit point are *not*
+carried out.
 
 In Vertical-First Mode, the `ALL` bit should
 not be used.  If set, behaviour is `UNDEFINED`.
@@ -146,7 +147,6 @@ Available options to combine:
 Pseudocode for Horizontal-First Mode:
 
 ```
-   
     cond_ok = not SVRMmode.ALL
     for srcstep in range(VL):
         new_srcstep, CRbits = SVSTATE_NEXT(srcstep)