From: tvijlbrief@8f4aa443232130439ed134e0d8e213b8cec69547 <tvijlbrief@web>
Date: Sun, 17 May 2020 10:22:13 +0000 (+0100)
Subject: Add git "submodule init" and "submodule update" for soc
X-Git-Tag: convert-csv-opcode-to-binary~2643
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=41da9cd12285f4d07306b4e9117c0942d856c8f3;p=libreriscv.git

Add git "submodule init" and "submodule update" for soc
---

diff --git a/index.mdwn b/index.mdwn
index cd6ec735e..079637f4e 100644
--- a/index.mdwn
+++ b/index.mdwn
@@ -119,7 +119,7 @@ Here is an example process of how to play with the soc code:
     
     cd nmutil; pip3 install -e .; cd ..
     cd ieee754fpu; pip3 install -e .; cd ..
-    cd soc; pip3 install -e .; cd ..
+    cd soc; git submodule init; git submodule update; pip3 install -e .; cd ..
     
     python3 soc/src/soc/decoder/power_decoder.py
     yosys -p "read_ilang decoder.il; show dec31"