From: lkcl Date: Wed, 23 Dec 2020 01:18:35 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1020 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=41f1ca9734d06a1f75aa1cd643d659dd9bf148b2;p=libreriscv.git --- diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn index ea7cbc9d3..7d7acbe48 100644 --- a/openpower/sv/vector_ops.mdwn +++ b/openpower/sv/vector_ops.mdwn @@ -3,9 +3,10 @@ The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example. This section includes such examples. Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors) However some of these actually could be added to a scalar ISA as bitmanipulation instructions. These are separated out into their own section. -Instructions suited to 3D GPU workloads (dotproduct, crossproduct, normalise) are out of scope: this document is for more general-purpose instructions that underpin and are critical to general-purpose Vector workloads (including GPU and VPU) -. +* Instructions suited to 3D GPU workloads (dotproduct, crossproduct, normalise) are out of scope: this document is for more general-purpose instructions that underpin and are critical to general-purpose Vector workloads (including GPU and VPU) +* Instructions related to the adaptation of CRs for use as predicate masks are covered separately, by crweird operations. See [[sv/cr_int_predication]]. + Links: *