From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 21 Jan 2022 15:15:52 +0000 (+0000)
Subject: grr, save/restore in verilator, use class member os.read/write
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=420a43825fbfa8547e2bd7362861a3d392f1cbe3;p=microwatt.git

grr, save/restore in verilator, use class member os.read/write
not daft "<<" or ">>" operator-overload
---

diff --git a/Makefile b/Makefile
index 387ce00..e4a46ea 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,7 @@
 GHDL ?= ghdl
 GHDLFLAGS=--std=08 -frelaxed
 CFLAGS=-O3 -Wall
+CXXFLAGS=-g -g
 
 GHDLSYNTH ?= ghdl.so
 YOSYS     ?= yosys
@@ -226,7 +227,7 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE)
 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
 # --top-module toplevel
 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
-	verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" \
+	verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY) -I../verilator" \
     --assert \
     --cc microwatt.v \
     --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c \
diff --git a/verilator/microwatt-verilator.cpp b/verilator/microwatt-verilator.cpp
index 5c91f92..8f30f0f 100644
--- a/verilator/microwatt-verilator.cpp
+++ b/verilator/microwatt-verilator.cpp
@@ -8,7 +8,7 @@
 #include "Vmicrowatt.h"
 #include "verilated.h"
 #include "verilated_vcd_c.h"
-#include "uart-verilated.h"
+#include "uart-verilator.h"
 
 /*
  * Current simulation time
@@ -72,7 +72,7 @@ void save_model(vluint64_t time, Vmicrowatt* topp)
 
     os.open(fname);
     os << main_time;  // user code must save the timestamp, etc
-    os << *uart;
+    os.write(uart, sizeof(*uart));
     os << *topp;
 }
 
@@ -84,7 +84,7 @@ void restore_model(vluint64_t time, Vmicrowatt* topp)
     struct uart_tx_state uart;
     os.open(fname);
     os >> main_time;
-    os >> uart;
+    os.read(&uart, sizeof(uart));
     os >> *topp;
     uart_restore(&uart);
 }