From: Wolfgang Gellerich Date: Tue, 20 Oct 2009 08:16:23 +0000 (+0000) Subject: s390.md: Added agen condition to operand forwarding bypasses. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=421b1e6b16e2cba4037fc7ceb6962d950bfe2873;p=gcc.git s390.md: Added agen condition to operand forwarding bypasses. 2009-10-20 Wolfgang Gellerich * config/s390/s390.md: Added agen condition to operand forwarding bypasses. Added bypass for early address generation use of int results. Updated comments. From-SVN: r153006 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 97e0d104d98..1bc1f04dc7f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2009-10-20 Wolfgang Gellerich + + * config/s390/s390.md: Added agen condition to operand + forwarding bypasses. + Added bypass for early address generation use of int results. + Updated comments. + 2009-10-20 Stefan Dösinger * config/i386/i386.c: Remove signal.h #include. diff --git a/gcc/config/s390/2097.md b/gcc/config/s390/2097.md index eb7240effd4..56893596a74 100644 --- a/gcc/config/s390/2097.md +++ b/gcc/config/s390/2097.md @@ -57,7 +57,8 @@ z10_int_fr_A3" "z10_other_super, z10_other_super_c_E1, z10_other_super_E1, \ z10_int_super, z10_int_super_E1, \ - z10_lr, z10_store_super") + z10_lr, z10_store_super" + " ! s390_agen_dep_p") ; Forwarding from z10_super to frz10_ and z10_rec. @@ -68,7 +69,8 @@ z10_store_super" "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \ z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \ - z10_other_fr_E1, z10_store_rec") + z10_other_fr_E1, z10_store_rec" + " ! s390_agen_dep_p") ; Forwarding from z10_fwd and z10_fr to z10_rec and z10_fr. @@ -84,7 +86,8 @@ z10_int_fr_A3" "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \ z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \ - z10_other_fr_E1, z10_store_rec") + z10_other_fr_E1, z10_store_rec" + " ! s390_agen_dep_p") ; @@ -205,15 +208,12 @@ (and (eq_attr "type" "lr") (eq_attr "z10prop" "z10_fr"))) "z10_e1_ANY, z10_Gate_ANY") -; "z10_e1_ANY") (define_insn_reservation "z10_lr_fr_E1" 6 (and (eq_attr "cpu" "z10") (and (eq_attr "type" "lr") (eq_attr "z10prop" "z10_fr_E1"))) "z10_e1_ANY, z10_Gate_ANY") -; "z10_e1_ANY") - (define_insn_reservation "z10_la" 6 (and (eq_attr "cpu" "z10") @@ -227,14 +227,12 @@ (and (eq_attr "type" "la") (eq_attr "z10prop" "z10_fwd"))) "z10_e1_ANY, z10_Gate_ANY") -; "z10_e1_ANY") (define_insn_reservation "z10_la_fwd_A1" 6 (and (eq_attr "cpu" "z10") (and (eq_attr "type" "la") (eq_attr "z10prop" "z10_fwd_A1"))) "z10_e1_ANY, z10_Gate_ANY") -; "z10_e1_ANY") ; larl-type instructions @@ -666,13 +664,14 @@ ; Address-related bypasses ; -; Here is the cycle diagram for Address-related bypasses: +; Here is the cycle diagram for address-related bypasses: ; ... G1 G2 G3 A0 A1 A2 A3 E1 P1 P2 P3 R0 ... -; ^ ^ ^ ^ ^ -; | | | | E1-type bypasses provide the new addr AFTER this cycle -; | | | A3-type bypasses provide the new addr AFTER this cycle -; | | A1-type bypasses provide the new addr AFTER this cycle -; | AGI resolution, actual USE of address is DURING this cycle +; ^ ^ ^ ^ ^ ^ +; | | | | | without bypass, its available AFTER this cycle +; | | | | E1-type bypasses provide the new value AFTER this cycle +; | | | A3-type bypasses provide the new value AFTER this cycle +; | | A1-type bypasses provide the new value AFTER this cycle +; | AGI resolution, actual USE of new value is DURING this cycle ; AGI detection (define_bypass 3 "z10_larl_A1, z10_la_fwd_A1, z10_other_fwd_A1, \ @@ -682,7 +681,6 @@ z10_cs, z10_stm, z10_other" "s390_agen_dep_p") - (define_bypass 5 "z10_larl_fwd_A3, z10_load_fwd_A3, z10_other_fwd_A3, \ z10_other_fr_A3, z10_int_fwd_A3, z10_int_fr_A3" "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ @@ -699,6 +697,12 @@ z10_cs, z10_stm, z10_other" "s390_agen_dep_p") +(define_bypass 9 "z10_int_super, z10_int_fwd, z10_int_fr" + "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ + z10_store, \ + z10_cs, z10_stm, z10_other" + "s390_agen_dep_p") + ;