From: Ali Saidi <saidi@eecs.umich.edu>
Date: Thu, 8 Nov 2007 15:46:41 +0000 (-0500)
Subject: TimingSimpleCPU: Add some DPRINTFs when the cpu suspends and resumes.
X-Git-Tag: m5_2.0_beta5~95
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=422ab8bec0034a6b703578ec2c92350c6382875a;p=gem5.git

TimingSimpleCPU: Add some DPRINTFs when the cpu suspends and resumes.

--HG--
extra : convert_revision : a305cf9dcaca5ed3b97499a5e24c511f4416125a
---

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 998d0b017..8d6a169ab 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -157,6 +157,7 @@ TimingSimpleCPU::drain(Event *drain_event)
 void
 TimingSimpleCPU::resume()
 {
+    DPRINTF(SimpleCPU, "Resume\n");
     if (_status != SwitchedOut && _status != Idle) {
         assert(system->getMemoryMode() == Enums::timing);
 
@@ -215,6 +216,8 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 void
 TimingSimpleCPU::activateContext(int thread_num, int delay)
 {
+    DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
+
     assert(thread_num == 0);
     assert(thread);
 
@@ -231,6 +234,8 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
 void
 TimingSimpleCPU::suspendContext(int thread_num)
 {
+    DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
+
     assert(thread_num == 0);
     assert(thread);
 
@@ -511,6 +516,8 @@ TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 void
 TimingSimpleCPU::fetch()
 {
+    DPRINTF(SimpleCPU, "Fetch\n");
+
     if (!curStaticInst || !curStaticInst->isDelayedCommit())
         checkForInterrupts();
 
@@ -560,6 +567,8 @@ TimingSimpleCPU::advanceInst(Fault fault)
 void
 TimingSimpleCPU::completeIfetch(PacketPtr pkt)
 {
+    DPRINTF(SimpleCPU, "Complete ICache Fetch\n");
+
     // received a response from the icache: execute the received
     // instruction
     assert(!pkt->isError());