From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 29 Apr 2022 12:35:02 +0000 (+0200)
Subject: Ignore merging past ffs that we are not properly merging
X-Git-Tag: yosys-0.17~17^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=422db937d44c10b850b8722dd39062650cf2db2b;p=yosys.git

Ignore merging past ffs that we are not properly merging
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 284d5db31..d19d837ff 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -987,6 +987,7 @@ void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates)
 
 	for (auto cell : candidates)
 	{
+		if (cell->type != ID($dff)) continue;
 		SigBit clock = cell->getPort(ID::CLK);
 		bool clock_pol = cell->getParam(ID::CLK_POLARITY).as_bool();
 		database[make_pair(clock, int(clock_pol))].insert(cell);