From: Luke Kenneth Casson Leighton Date: Wed, 30 Sep 2020 11:47:37 +0000 (+0100) Subject: add more debug prints in icache X-Git-Tag: 24jan2021_ls180~269 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=422de550a25533f8a5cb3bcaef5d7a3efcd3554c;p=soc.git add more debug prints in icache --- diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index ad49a417..bf5f43fc 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -576,10 +576,10 @@ class ICache(Elaboratable): # Generate a cache RAM for each way def rams(self, m, r, cache_out_row, use_previous, replace_way, req_row): comb = m.d.comb + sync = m.d.sync wb_in, stall_in = self.wb_in, self.stall_in - for i in range(NUM_WAYS): do_read = Signal(name="do_rd_%d" % i) do_write = Signal(name="do_wr_%d" % i) @@ -601,8 +601,16 @@ class ICache(Elaboratable): comb += do_read.eq(~(stall_in | use_previous)) comb += do_write.eq(wb_in.ack & (replace_way == i)) + with m.If(do_write): + sync += Display("cache write adr: %x data: %x", + wr_addr, way.wr_data) + with m.If(r.hit_way == i): comb += cache_out_row.eq(d_out) + with m.If(do_read): + sync += Display("cache read adr: %x data: %x", + req_row, d_out) + comb += rd_addr.eq(req_row) comb += wr_addr.eq(r.store_row) comb += wr_sel.eq(Repl(do_write, ROW_SIZE))