From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 11 May 2015 19:38:06 +0000 (+0200)
Subject: Merge pull request #63 from wluker/verilog-backend-mem
X-Git-Tag: yosys-0.6~295
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=42348cddd9218f198e93bc11909e7b118a71c9ba;p=yosys.git

Merge pull request #63 from wluker/verilog-backend-mem

Fixed bug in $mem cell verilog code generation.
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42348cddd9218f198e93bc11909e7b118a71c9ba