From: Florent Kermarrec Date: Thu, 21 May 2020 07:14:33 +0000 (+0200) Subject: platforms/targets: keep in sync with litex-boards. X-Git-Tag: 24jan2021_ls180~306 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=42350f6d83298f1dc1a40e192295ffb1273b8a6a;p=litex.git platforms/targets: keep in sync with litex-boards. - LedChaser. - use of soc.build_name in load/flash bitstream. --- diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py index 1f8101d4..7f21fac8 100644 --- a/litex/boards/platforms/arty.py +++ b/litex/boards/platforms/arty.py @@ -145,6 +145,16 @@ _io = [ ), ] +_sdcard_pmod_io = [ # https://store.digilentinc.com/pmod-microsd-microsd-card-slot/ + ("sdcard", 0, + Subsignal("data", Pins("D15 J17 J18 E15")), + Subsignal("cmd", Pins("E16")), + Subsignal("clk", Pins("C15")), + Subsignal("cd", Pins("K15")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ), +] + # Connectors --------------------------------------------------------------------------------------- _connectors = [ diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 29e33bc3..98d2e3be 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -15,6 +15,7 @@ from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser from litedram.modules import MT41K128M16 from litedram.phy import s7ddrphy @@ -94,6 +95,12 @@ class BaseSoC(SoCCore): self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy) + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = Cat(*[platform.request("user_led", i) for i in range(4)]), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + # Build -------------------------------------------------------------------------------------------- def main(): @@ -115,7 +122,7 @@ def main(): if args.load: prog = soc.platform.create_programmer() - prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index 960dc48e..4cfb845d 100755 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -17,6 +17,7 @@ from litex.soc.cores.clock import CycloneIVPLL from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser from litedram.modules import IS42S16160 from litedram.phy import GENSDRPHY @@ -67,6 +68,12 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = Cat(*[platform.request("user_led", i) for i in range(8)]), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + # Build -------------------------------------------------------------------------------------------- def main(): @@ -83,7 +90,7 @@ def main(): if args.load: prog = soc.platform.create_programmer() - prog.load_bitstream(os.path.join(builder.gateware_dir, "top.sof")) + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index d0b33def..4e5e823b 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -14,6 +14,7 @@ from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser from litedram.modules import MT41J256M16 from litedram.phy import s7ddrphy @@ -85,6 +86,12 @@ class BaseSoC(SoCCore): self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy) + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = Cat(*[platform.request("user_led", i) for i in range(8)]), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + # Build -------------------------------------------------------------------------------------------- def main(): @@ -105,7 +112,7 @@ def main(): if args.load: prog = soc.platform.create_programmer() - prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/icebreaker.py b/litex/boards/targets/icebreaker.py index ae1363b9..5563a7e4 100755 --- a/litex/boards/targets/icebreaker.py +++ b/litex/boards/targets/icebreaker.py @@ -130,7 +130,7 @@ def main(): if args.load: prog = soc.platform.create_programmer() - prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bin")) + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bin")) if args.flash: flash(args.bios_flash_offset) diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 9bca1582..e40492a7 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -16,6 +16,7 @@ from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser from litedram.modules import MT8JTF12864 from litedram.phy import s7ddrphy @@ -80,6 +81,12 @@ class BaseSoC(SoCCore): self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = Cat(*[platform.request("user_led", i) for i in range(8)]), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + # Build -------------------------------------------------------------------------------------------- def main(): @@ -97,7 +104,7 @@ def main(): if args.load: prog = soc.platform.create_programmer() - prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index 138f3ffa..79755cde 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -14,6 +14,7 @@ from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser from litedram.modules import EDY4016A from litedram.phy import usddrphy @@ -88,6 +89,12 @@ class BaseSoC(SoCCore): self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]") self.add_ethernet(phy=self.ethphy) + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = Cat(*[platform.request("user_led", i) for i in range(8)]), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + # Build -------------------------------------------------------------------------------------------- def main(): @@ -105,7 +112,7 @@ def main(): if args.load: prog = soc.platform.create_programmer() - prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py index 641e1119..a14ab5e5 100755 --- a/litex/boards/targets/minispartan6.py +++ b/litex/boards/targets/minispartan6.py @@ -20,6 +20,7 @@ from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser from litedram.modules import AS4C16M16 from litedram.phy import GENSDRPHY @@ -66,6 +67,12 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = Cat(*[platform.request("user_led", i) for i in range(8)]), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + # Build -------------------------------------------------------------------------------------------- def main(): @@ -82,7 +89,7 @@ def main(): if args.load: prog = soc.platform.create_programmer() - prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index 91662f2e..335d447f 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -14,7 +14,7 @@ from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * -from litex.soc.integration.soc import * +from litex.soc.cores.led import LedChaser from litedram.modules import K4B2G1646F from litedram.phy import s7ddrphy @@ -82,6 +82,12 @@ class BaseSoC(SoCCore): self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = Cat(*[platform.request("user_led", i) for i in range(6)]), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + # Build -------------------------------------------------------------------------------------------- def main(): @@ -99,7 +105,7 @@ def main(): if args.load: prog = soc.platform.create_programmer() - prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index e608963f..decaf738 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -14,6 +14,7 @@ from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser from litedram.modules import MT47H64M16 from litedram.phy import s7ddrphy @@ -86,6 +87,12 @@ class BaseSoC(SoCCore): self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = Cat(*[platform.request("user_led", i) for i in range(16)]), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + def add_sdcard(self): sdcard_pads = self.platform.request("sdcard") if hasattr(sdcard_pads, "rst"): @@ -142,7 +149,7 @@ def main(): if args.load: prog = soc.platform.create_programmer() - prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index f53a0bfa..f5ad3697 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -14,6 +14,7 @@ from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser from litedram.modules import MT41K256M16 from litedram.phy import s7ddrphy @@ -80,6 +81,12 @@ class BaseSoC(SoCCore): self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = Cat(*[platform.request("user_led", i) for i in range(8)]), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + # Build -------------------------------------------------------------------------------------------- def main(): @@ -97,7 +104,7 @@ def main(): if args.load: prog = soc.platform.create_programmer() - prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 9802266c..20ae17d3 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -21,6 +21,7 @@ from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser from litedram import modules as litedram_modules from litedram.phy import GENSDRPHY @@ -89,6 +90,12 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = Cat(*[platform.request("user_led", i) for i in range(8)]), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + # Build -------------------------------------------------------------------------------------------- def main(): @@ -114,7 +121,7 @@ def main(): if args.load: prog = soc.platform.create_programmer() - prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf")) + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index e390575f..e07f60e3 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -18,6 +18,7 @@ from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser from litedram.modules import MT41K64M16 from litedram.phy import ECP5DDRPHY @@ -106,6 +107,12 @@ class BaseSoC(SoCCore): self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = Cat(*[platform.request("user_led", i) for i in range(8)]), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + # Build -------------------------------------------------------------------------------------------- def main(): @@ -127,7 +134,7 @@ def main(): if args.load: prog = soc.platform.create_programmer() - prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf")) + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf")) if __name__ == "__main__": main()