From: Raptor Engineering Development Team <support@raptorengineering.com>
Date: Sun, 10 Apr 2022 02:31:27 +0000 (-0500)
Subject: Put sysclk2x back under system reset control
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=423fdc3682f2b3a6c30df46af92e0f7aac617797;p=gram.git

Put sysclk2x back under system reset control
---

diff --git a/examples/ecp5_crg.py b/examples/ecp5_crg.py
index 82ff66d..cda8a99 100644
--- a/examples/ecp5_crg.py
+++ b/examples/ecp5_crg.py
@@ -219,7 +219,7 @@ class ECP5CRG(Elaboratable):
         m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~pod_done|~reset)
 
         # Generating sync2x (200Mhz) and init (25Mhz) from extclk
-        cd_sync2x = ClockDomain("sync2x", local=False, reset_less=True)
+        cd_sync2x = ClockDomain("sync2x", local=False)
         cd_sync2x_unbuf = ClockDomain("sync2x_unbuf",
                                       local=False, reset_less=True)
         cd_init = ClockDomain("init", local=False)