From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 26 Nov 2018 11:19:14 +0000 (+0000)
Subject: prepare get_fetch_action for move to separate module
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4241bfc8748809f4cbf0ae437ef9bbdd7a62e0c4;p=rv32.git

prepare get_fetch_action for move to separate module
---

diff --git a/cpu.py b/cpu.py
index 5206b34..ff46452 100644
--- a/cpu.py
+++ b/cpu.py
@@ -190,7 +190,8 @@ class Fetch:
         self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
         self.output_state = Signal(fetch_output_state,name="fetch_output_state")
 
-    def get_fetch_action(self, dc, load_store_misaligned, mi,
+    def get_fetch_action(self, dc_act, load_store_misaligned, mi_rw_wait,
+                         mi_rw_address_valid,
                          branch_taken, misaligned_jump_target,
                          csr_op_is_valid):
         c = {}
@@ -199,19 +200,19 @@ class Fetch:
         c[FOS.trap] = self.action.eq(FA.ack_trap)
 
         # illegal instruction -> error trap
-        i= If((dc.act & DA.trap_illegal_instruction) != 0,
+        i= If((dc_act & DA.trap_illegal_instruction) != 0,
                  self.action.eq(FA.error_trap)
               )
 
         # ecall / ebreak -> noerror trap
-        i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
+        i = i.Elif((dc_act & DA.trap_ecall_ebreak) != 0,
                  self.action.eq(FA.noerror_trap))
 
         # load/store: check alignment, check wait
-        i = i.Elif((dc.act & (DA.load | DA.store)) != 0,
-                If((load_store_misaligned | ~mi.rw_address_valid),
+        i = i.Elif((dc_act & (DA.load | DA.store)) != 0,
+                If((load_store_misaligned | ~mi_rw_address_valid),
                     self.action.eq(FA.error_trap) # misaligned or invalid addr
-                ).Elif(mi.rw_wait,
+                ).Elif(mi_rw_wait,
                     self.action.eq(FA.wait) # wait
                 ).Else(
                     self.action.eq(FA.default) # ok
@@ -219,11 +220,11 @@ class Fetch:
               )
 
         # fence
-        i = i.Elif((dc.act & DA.fence) != 0,
+        i = i.Elif((dc_act & DA.fence) != 0,
                  self.action.eq(FA.fence))
 
         # branch -> misaligned=error, otherwise jump
-        i = i.Elif((dc.act & DA.branch) != 0,
+        i = i.Elif((dc_act & DA.branch) != 0,
                 If(branch_taken,
                     If(misaligned_jump_target,
                         self.action.eq(FA.error_trap)
@@ -236,7 +237,7 @@ class Fetch:
               )
 
         # jal/jalr -> misaligned=error, otherwise jump
-        i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
+        i = i.Elif((dc_act & (DA.jal | DA.jalr)) != 0,
                 If(misaligned_jump_target,
                     self.action.eq(FA.error_trap)
                 ).Else(
@@ -245,7 +246,7 @@ class Fetch:
               )
 
         # csr -> opvalid=ok, else error trap
-        i = i.Elif((dc.act & DA.csr) != 0,
+        i = i.Elif((dc_act & DA.csr) != 0,
                 If(csr_op_is_valid,
                     self.action.eq(FA.default)
                 ).Else(
@@ -829,7 +830,8 @@ class CPU(Module):
         # CSR decoding
         csr = CSR(self.comb, self.sync, dc, self.regs.rs1)
 
-        self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi,
+        self.comb += ft.get_fetch_action(dc.act, load_store_misaligned,
+                                 mi.rw_wait, mi.rw_address_valid,
                                  branch_taken, misaligned_jump_target,
                                  csr.op_is_valid)