From: lkcl <lkcl@web>
Date: Fri, 30 Aug 2019 10:36:40 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4187
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=424339d972f1c136feea7357fcb5ffc96e14e511;p=libreriscv.git

---

diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn
index e65cefce1..15d7d11d6 100644
--- a/simple_v_extension/specification/sv.setvl.mdwn
+++ b/simple_v_extension/specification/sv.setvl.mdwn
@@ -7,11 +7,11 @@ Thus it makes more sense to actually *use* one of the scalar registers *as* VL.
 
 Format for Vector Configuration Instructions under OP-V major opcode:
 
-| 31|30   20|19    15|14   12|11 7|6     0| name       |
-|---|-------|--------|-------|----|-------|------------|
-| 0 | VLMAX | rs1    | 1 1 1 | rd |1010111| sv.setvl   |
-| 0 | VLMAX | 0 (x0) | 1 1 1 | rd |1010111| sv.setvl   |
-| 1 | --    | --     | 1 1 1 | -- |1010111| *reserved* |
+| 31|30   20|19    15|14..12|11 7|6     0| name       |
+|---|-------|--------|------|----|-------|------------|
+| 0 | VLMAX | rs1    | 111  | rd |1010111| sv.setvl   |
+| 0 | VLMAX | 0 (x0) | 111  | rd |1010111| sv.setvl   |
+| 1 | --    | --     | 111  | -- |1010111| *reserved* |
 
 
 # pseudocode