From: lkcl <lkcl@web>
Date: Mon, 2 Aug 2021 09:42:23 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~537
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=42447f08fe4e7aec70b0fbbf80323a51b307139f;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index c42f3df89..baff71632 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -118,9 +118,9 @@ Pseudocode for Horizontal-First Mode:
        cond_ok = 1
    else
        cond_ok = not SVRMmode.ALL
-       for i in range(VL):
+       for srcstep in range(VL):
            # select predicate bit or zero/one
-           if predicate[i]:
+           if predicate[srcstep]:
                testbit = CR[BI+32+srcstep*4]
            else if not SVRMmode.sz:
                continue
@@ -136,9 +136,9 @@ Pseudocode for Horizontal-First Mode:
            # test for VL to be set (and exit)
            if ~el_cond_ok and VLSET
                if SVRMmode.VLI
-                   SVSTATE.VL = i+1
+                   SVSTATE.VL = srcstep+1
                else
-                   SVSTATE.VL = i
+                   SVSTATE.VL = srcstep
                break
            # early exit? 
            if SVRMmode.ALL: