From: lkcl <lkcl@web>
Date: Thu, 4 May 2023 18:28:58 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4248b7be03b88499262913023215722d76ca21c1;p=libreriscv.git

---

diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index efa246d07..75cc582d2 100644
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -247,18 +247,18 @@ zero because there is no encoding space to select between -1, 0 and 1, and
 # Pack/Unpack Mode:
 
 It is possible to apply Pack and Unpack to Vectorised 
-swizzle moves, and these instructions are of EXTRA type
-`RM-2P-1S1D-PU`. The interaction requires specific explanation
+swizzle moves. The interaction requires specific explanation
 because it involves the separate SUBVLs (with destination SUBVL
 being separate). Key to understanding is that the 
 source and
 destination SUBVL be "outer" loops instead of inner loops,
 exactly as in [[sv/remap]] Matrix mode, under the control
-of `PACK_en` and `UNPACK_en`.
+of `SVSTATE.PACK` and `SVSTATE.UNPACK`.
 
 Illustrating a
 "normal" SVP64 operation with `SUBVL!=1` (assuming no elwidth overrides):
 
+```
     def index():
         for i in range(VL):
             for j in range(SUBVL):
@@ -266,9 +266,11 @@ Illustrating a
 
     for idx in index():
         operation_on(RA+idx)
+```
 
 For a separate source/dest SUBVL (again, no elwidth overrides):
 
+```
     # yield an outer-SUBVL or inner VL loop with SUBVL
     def index_dest(outer):
         if outer:
@@ -290,6 +292,7 @@ For a separate source/dest SUBVL (again, no elwidth overrides):
             for i in range(VL):
                 for j in range(SUBVL):
                     ....
+```
 
 "yield" from python is used here for simplicity and clarity.
 The two Finite State Machines for the generation of the source