From: Michael Meissner Date: Wed, 7 Feb 2018 22:54:59 +0000 (+0000) Subject: re PR target/84154 (PowerPC GCC 7 and 8 have regression in converting fp to short... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4253435ecaf28bfc387407dd5a2fb4f4283ed203;p=gcc.git re PR target/84154 (PowerPC GCC 7 and 8 have regression in converting fp to short/char and returning it) [gcc] 2018-02-07 Michael Meissner PR target/84154 * config/rs6000/rs6000.md (fix_trunc2): Convert from define_expand to be define_insn_and_split. Rework float/double/_Float128 conversions to QI/HI/SImode to work with both ISA 2.07 (power8) or ISA 3.0 (power9). Fix regression where conversions to QI/HImode types did a store and then a load to truncate the value. For conversions to VSX registers, don't split the insn, instead emit the code directly. Use the code iterator any_fix to combine signed and unsigned conversions. (fix_truncsi2_p8): Likewise. (fixuns_trunc2): Likewise. (fix_trunc2): Likewise. (fix_trunc2): Likewise. (fix_di2_hw): Likewise. (fixuns_di2_hw): Likewise. (fix_si2_hw): Likewise. (fixuns_si2_hw): Likewise. (fix_2_hw): Likewise. (fix_trunc2): Likewise. (fctiwz__smallint): Rename fctiwz__smallint to fix_truncsi2_p8. (fix_trunc2_internal): Delete, no longer used. (fixuns_trunc2_internal): Likewise. (fix__mem): Likewise. (fctiwz__mem): Likewise. (fix__mem): Likewise. (fix_trunc2_mem): On ISA 3.0, prevent the register allocator from doing a direct move to the GPRs to do a store, and instead use the ISA 3.0 store byte/half-word from vector register instruction. For IEEE 128-bit floating point, also optimize stores of 32-bit ints. (fix_trunc2_mem): Likewise. [gcc/testsuite] 2018-02-07 Michael Meissner PR target/84154 * gcc.target/powerpc/pr84154-1.c: New tests. * gcc.target/powerpc/pr84154-2.c: Likewise. * gcc.target/powerpc/pr84154-3.c: Likewise. From-SVN: r257470 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bcd892c8b3c..59e1f8fada8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,39 @@ +2018-02-07 Michael Meissner + + PR target/84154 + * config/rs6000/rs6000.md (fix_trunc2): + Convert from define_expand to be define_insn_and_split. Rework + float/double/_Float128 conversions to QI/HI/SImode to work with + both ISA 2.07 (power8) or ISA 3.0 (power9). Fix regression where + conversions to QI/HImode types did a store and then a load to + truncate the value. For conversions to VSX registers, don't split + the insn, instead emit the code directly. Use the code iterator + any_fix to combine signed and unsigned conversions. + (fix_truncsi2_p8): Likewise. + (fixuns_trunc2): Likewise. + (fix_trunc2): Likewise. + (fix_trunc2): Likewise. + (fix_di2_hw): Likewise. + (fixuns_di2_hw): Likewise. + (fix_si2_hw): Likewise. + (fixuns_si2_hw): Likewise. + (fix_2_hw): Likewise. + (fix_trunc2): Likewise. + (fctiwz__smallint): Rename fctiwz__smallint to + fix_truncsi2_p8. + (fix_trunc2_internal): Delete, no longer + used. + (fixuns_trunc2_internal): Likewise. + (fix__mem): Likewise. + (fctiwz__mem): Likewise. + (fix__mem): Likewise. + (fix_trunc2_mem): On ISA 3.0, prevent + the register allocator from doing a direct move to the GPRs to do + a store, and instead use the ISA 3.0 store byte/half-word from + vector register instruction. For IEEE 128-bit floating point, + also optimize stores of 32-bit ints. + (fix_trunc2_mem): Likewise. + 2018-02-07 Alan Hayward * genextract.c (push_pathstr_operand): New function to support diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index f085f0da7bd..33f0d959f5d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5700,43 +5700,59 @@ xscvdpsxds %x0,%x1" [(set_attr "type" "fp")]) -(define_expand "fix_trunc2" - [(parallel [(set (match_operand: 0 "nonimmediate_operand") - (fix:QHI (match_operand:SFDF 1 "gpc_reg_operand"))) - (clobber (match_scratch:DI 2))])] - "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT" +;; If we have ISA 3.0, QI/HImode values can go in both VSX registers and GPR +;; registers. If we have ISA 2.07, we don't allow QI/HImode values in the +;; vector registers, so we need to do direct moves to the GPRs, but SImode +;; values can go in VSX registers. Keeping the direct move part through +;; register allocation prevents the register allocator from doing a direct move +;; of the SImode value to a GPR, and then a store/load. +(define_insn_and_split "fix_trunc2" + [(set (match_operand: 0 "gpc_reg_operand" "=wJ,wJwK,r") + (any_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand" "wJ,wJwK,wa"))) + (clobber (match_scratch:SI 2 "=X,X,wi"))] + "TARGET_DIRECT_MOVE" + "@ + fctiwz %0,%1 + xscvdpxws %x0,%x1 + #" + "&& reload_completed && int_reg_operand (operands[0], mode)" + [(set (match_dup 2) + (any_fix:SI (match_dup 1))) + (set (match_dup 3) + (match_dup 2))] { - if (MEM_P (operands[0])) - operands[0] = rs6000_address_for_fpconvert (operands[0]); -}) + operands[3] = gen_rtx_REG (SImode, REGNO (operands[0])); +} + [(set_attr "length" "4,4,8") + (set_attr "type" "fp")]) + +(define_insn "*fix_truncsi2_p8" + [(set (match_operand:SI 0 "gpc_reg_operand" "=d,wa") + (any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")))] + "TARGET_DIRECT_MOVE" + "@ + fctiwz %0,%1 + xscvdpxws %x0,%x1" + [(set_attr "type" "fp")]) -(define_insn_and_split "*fix_trunc2_internal" - [(set (match_operand: 0 "reg_or_indexed_operand" "=wIwJ,rZ") - (fix:QHI - (match_operand:SFDF 1 "gpc_reg_operand" ","))) - (clobber (match_scratch:DI 2 "=X,wi"))] - "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT" +;; Keep the convert and store together through register allocation to prevent +;; the register allocator from getting clever and doing a direct move to a GPR +;; and then store for reg+offset stores. +(define_insn_and_split "*fix_trunc2_mem" + [(set (match_operand:QHSI 0 "memory_operand" "=Z") + (any_fix:QHSI (match_operand:SFDF 1 "gpc_reg_operand" "wa"))) + (clobber (match_scratch:SI 2 "=wa"))] + "(mode == SImode && TARGET_P8_VECTOR) || TARGET_P9_VECTOR" "#" "&& reload_completed" - [(const_int 0)] + [(set (match_dup 2) + (any_fix:SI (match_dup 1))) + (set (match_dup 0) + (match_dup 3))] { - rtx dest = operands[0]; - rtx src = operands[1]; - - if (vsx_register_operand (dest, mode)) - { - rtx di_dest = gen_rtx_REG (DImode, REGNO (dest)); - emit_insn (gen_fix_truncdi2 (di_dest, src)); - } - else - { - rtx tmp = operands[2]; - rtx tmp2 = gen_rtx_REG (mode, REGNO (tmp)); - - emit_insn (gen_fix_truncdi2 (tmp, src)); - emit_move_insn (dest, tmp2); - } - DONE; + operands[3] = (mode == SImode + ? operands[2] + : gen_rtx_REG (mode, REGNO (operands[2]))); }) (define_expand "fixuns_truncsi2" @@ -5803,71 +5819,6 @@ xscvdpuxds %x0,%x1" [(set_attr "type" "fp")]) -(define_expand "fixuns_trunc2" - [(parallel [(set (match_operand: 0 "nonimmediate_operand") - (unsigned_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand"))) - (clobber (match_scratch:DI 2))])] - "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT" -{ - if (MEM_P (operands[0])) - operands[0] = rs6000_address_for_fpconvert (operands[0]); -}) - -(define_insn_and_split "*fixuns_trunc2_internal" - [(set (match_operand: 0 "reg_or_indexed_operand" "=wIwJ,rZ") - (unsigned_fix:QHI - (match_operand:SFDF 1 "gpc_reg_operand" ","))) - (clobber (match_scratch:DI 2 "=X,wi"))] - "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(const_int 0)] -{ - rtx dest = operands[0]; - rtx src = operands[1]; - - if (vsx_register_operand (dest, mode)) - { - rtx di_dest = gen_rtx_REG (DImode, REGNO (dest)); - emit_insn (gen_fixuns_truncdi2 (di_dest, src)); - } - else - { - rtx tmp = operands[2]; - rtx tmp2 = gen_rtx_REG (mode, REGNO (tmp)); - - emit_insn (gen_fixuns_truncdi2 (tmp, src)); - emit_move_insn (dest, tmp2); - } - DONE; -}) - -;; If -mvsx-small-integer, we can represent the FIX operation directly. On -;; older machines, we have to use an UNSPEC to produce a SImode and move it -;; to another location, since SImode is not allowed in vector registers. -(define_insn "*fctiwz__smallint" - [(set (match_operand:SI 0 "vsx_register_operand" "=d,wi") - (any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" ",")))] - "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_P8_VECTOR" - "@ - fctiwz %0,%1 - xscvdpxws %x0,%x1" - [(set_attr "type" "fp")]) - -;; Combiner pattern to prevent moving the result of converting a floating point -;; value to 32-bit integer to GPR in order to save it. -(define_insn_and_split "*fctiwz__mem" - [(set (match_operand:SI 0 "memory_operand" "=Z") - (any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "wa"))) - (clobber (match_scratch:SI 2 "=wa"))] - "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_P8_VECTOR" - "#" - "&& reload_completed" - [(set (match_dup 2) - (any_fix:SI (match_dup 1))) - (set (match_dup 0) - (match_dup 2))]) - ;; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) ;; rather than (set (subreg:SI (reg)) (fix:SI ...)) ;; because the first makes it clear that operand 0 is not live @@ -14362,49 +14313,45 @@ (set_attr "length" "8")]) ;; Conversion between IEEE 128-bit and integer types -(define_insn "fix_di2_hw" - [(set (match_operand:DI 0 "altivec_register_operand" "=v") - (fix:DI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" - "xscvqpsdz %0,%1" - [(set_attr "type" "vecfloat") - (set_attr "size" "128")]) - -(define_insn "fixuns_di2_hw" - [(set (match_operand:DI 0 "altivec_register_operand" "=v") - (unsigned_fix:DI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" - "xscvqpudz %0,%1" - [(set_attr "type" "vecfloat") - (set_attr "size" "128")]) -(define_insn "fix_si2_hw" - [(set (match_operand:SI 0 "altivec_register_operand" "=v") - (fix:SI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" - "xscvqpswz %0,%1" +;; The fix function for DImode and SImode was declared earlier as a +;; define_expand. It calls into rs6000_expand_float128_convert if we don't +;; have IEEE 128-bit hardware support. QImode and HImode are not provided +;; unless we have the IEEE 128-bit hardware. +;; +;; Unlike the code for converting SFmode/DFmode to QImode/HImode, we don't have +;; to provide a GPR target that used direct move and a conversion in the GPR +;; which works around QImode/HImode not being allowed in vector registers in +;; ISA 2.07 (power8). +(define_insn "fix_2_hw" + [(set (match_operand:SDI 0 "altivec_register_operand" "=v") + (any_fix:SDI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "xscvqpz %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) -(define_insn "fixuns_si2_hw" - [(set (match_operand:SI 0 "altivec_register_operand" "=v") - (unsigned_fix:SI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" - "xscvqpuwz %0,%1" +(define_insn "fix_trunc2" + [(set (match_operand:QHI 0 "altivec_register_operand" "=v") + (any_fix:QHI + (match_operand:IEEE128 1 "altivec_register_operand" "v")))] + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "xscvqpwz %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) -;; Combiner pattern to prevent moving the result of converting an IEEE 128-bit -;; floating point value to 32-bit integer to GPR in order to save it. -(define_insn_and_split "*fix__mem" - [(set (match_operand:SI 0 "memory_operand" "=Z") - (any_fix:SI (match_operand:IEEE128 1 "altivec_register_operand" "v"))) - (clobber (match_scratch:SI 2 "=v"))] +;; Combiner patterns to prevent moving the result of converting an IEEE 128-bit +;; floating point value to 8/16/32-bit integer to GPR in order to save it. +(define_insn_and_split "*fix_trunc2_mem" + [(set (match_operand:QHSI 0 "memory_operand" "=Z") + (any_fix:QHSI + (match_operand:IEEE128 1 "altivec_register_operand" "v"))) + (clobber (match_scratch:QHSI 2 "=v"))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "#" "&& reload_completed" [(set (match_dup 2) - (any_fix:SI (match_dup 1))) + (any_fix:QHSI (match_dup 1))) (set (match_dup 0) (match_dup 2))]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5b59c80639e..3b61a967998 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2018-02-07 Michael Meissner + + PR target/84154 + * gcc.target/powerpc/pr84154-1.c: New tests. + * gcc.target/powerpc/pr84154-2.c: Likewise. + * gcc.target/powerpc/pr84154-3.c: Likewise. + 2018-02-07 Will Schmidt * gcc.target/powerpc/builtins-mergew-mergeow.c: Update dg-requires. diff --git a/gcc/testsuite/gcc.target/powerpc/pr84154-1.c b/gcc/testsuite/gcc.target/powerpc/pr84154-1.c new file mode 100644 index 00000000000..c7c61be0def --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr84154-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2" } */ + +/* PR target/84154. Make sure conversion to char/short does not generate a + store and a load on ISA 2.07 and newer systems. */ + +unsigned char +double_to_uc (double x) +{ + return x; +} + +signed char +double_to_sc (double x) +{ + return x; +} + +unsigned short +double_to_us (double x) +{ + return x; +} + +short +double_to_ss (double x) +{ + return x; +} + +unsigned int +double_to_ui (double x) +{ + return x; +} + +int +double_to_si (double x) +{ + return x; +} + +/* { dg-final { scan-assembler-times {\mextsb\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mextsh\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mrlwinm\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlbz\M} } } */ +/* { dg-final { scan-assembler-not {\mlhz\M} } } */ +/* { dg-final { scan-assembler-not {\mlha\M} } } */ +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */ +/* { dg-final { scan-assembler-not {\mstw\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr84154-2.c b/gcc/testsuite/gcc.target/powerpc/pr84154-2.c new file mode 100644 index 00000000000..619777ce8dd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr84154-2.c @@ -0,0 +1,58 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-mcpu=power8 -O2" } */ + +/* PR target/84154. Make sure on ISA 2.07 (power8) that we store the result of + a conversion to char/short using an offsettable address does not generate + direct moves for storing 32-bit integers, but does do a direct move for + 8/16-bit integers. */ + +void +double_to_uc (double x, unsigned char *p) +{ + p[3] = x; +} + +void +double_to_sc (double x, signed char *p) +{ + p[3] = x; +} + +void +double_to_us (double x, unsigned short *p) +{ + p[3] = x; +} + +void +double_to_ss (double x, short *p) +{ + p[3] = x; +} + +void +double_to_ui (double x, unsigned int *p) +{ + p[3] = x; +} + +void +double_to_si (double x, int *p) +{ + p[3] = x; +} + +/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mstfiwx\M|\mstxsiwx\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstb\M} 2 } } */ +/* { dg-final { scan-assembler-times {\msth\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlbz\M} } } */ +/* { dg-final { scan-assembler-not {\mlhz\M} } } */ +/* { dg-final { scan-assembler-not {\mlha\M} } } */ +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */ +/* { dg-final { scan-assembler-not {\mstw\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr84154-3.c b/gcc/testsuite/gcc.target/powerpc/pr84154-3.c new file mode 100644 index 00000000000..0361e2f1b51 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr84154-3.c @@ -0,0 +1,60 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +/* PR target/84154. Make sure on ISA 3.0 we store the result of a conversion + to char/short using an offsettable address does not generate direct moves + for storing 8/16/32-bit integers. */ + +void +double_to_uc (double x, unsigned char *p) +{ + p[3] = x; +} + +void +double_to_sc (double x, signed char *p) +{ + p[3] = x; +} + +void +double_to_us (double x, unsigned short *p) +{ + p[3] = x; +} + +void +double_to_ss (double x, short *p) +{ + p[3] = x; +} + +void +double_to_ui (double x, unsigned int *p) +{ + p[3] = x; +} + +void +double_to_si (double x, int *p) +{ + p[3] = x; +} + +/* { dg-final { scan-assembler-times {\maddi\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mstfiwx\M|\mstxsiwx\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstxsibx\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstxsihx\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlbz\M} } } */ +/* { dg-final { scan-assembler-not {\mlhz\M} } } */ +/* { dg-final { scan-assembler-not {\mlha\M} } } */ +/* { dg-final { scan-assembler-not {\mmfvsrwz\M} } } */ +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */ +/* { dg-final { scan-assembler-not {\mstw\M} } } */ +/* { dg-final { scan-assembler-not {\mstb\M} } } */ +/* { dg-final { scan-assembler-not {\msth\M} } } */