From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Sep 2019 00:06:17 +0000 (-0700)
Subject: Get rid of sigPused
X-Git-Tag: working-ls180~1039^2~204
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=42548d979018c4bc3b71d4faa0900b18d2d290ec;p=yosys.git

Get rid of sigPused
---

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 4d2152f61..0d1937844 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -43,8 +43,6 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
 	log("postAdd:    %s\n", log_id(st.postAdd, "--"));
 	log("postAddMux: %s\n", log_id(st.postAddMux, "--"));
 	log("ffP:        %s\n", log_id(st.ffP, "--"));
-	//log("muxP:  %s\n", log_id(st.muxP, "--"));
-	log("sigPused:   %s\n", log_signal(st.sigPused));
 #endif
 
 	log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index c45e92d6f..375b5a492 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -19,8 +19,16 @@ code sigAset sigBset
 endcode
 
 code sigM
-	sigM = port(dsp, \P);
-	//if (GetSize(sigH) <= 10)
+	SigSpec P = port(dsp, \P);
+	// Only care about those bits that are used
+	int i;
+	for (i = 0; i < GetSize(P); i++) {
+		if (nusers(P[i]) <= 1)
+			break;
+		sigM.append(P[i]);
+	}
+	log_assert(nusers(P.extract_end(i)) <= 1);
+	//if (GetSize(sigM) <= 10)
 	//	reject;
 endcode
 
@@ -156,23 +164,14 @@ code sigC sigP
 	}
 endcode
 
-// Extract the bits of P that actually have a consumer
-// (as opposed to being a dummy)
-code sigPused
-	for (int i = 0; i < GetSize(sigP); i++)
-		if (sigP[i].wire && nusers(sigP[i]) > 1)
-			sigPused.append(sigP[i]);
-endcode
-
 match ffP
 	if param(dsp, \PREG).as_int() == 0
-	if !sigPused.empty()
-	if nusers(sigPused) == 2
 	select ffP->type.in($dff)
 	// DSP48E1 does not support clock inversion
 	select param(ffP, \CLK_POLARITY).as_bool()
-	filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused)
-	filter includes(port(ffP, \D).to_sigbit_set(), sigPused.to_sigbit_set())
+	filter GetSize(port(ffP, \D)) >= GetSize(sigP)
+	slice offset GetSize(port(ffP, \D))
+	filter offset+GetSize(sigP) <= GetSize(port(ffP, \D)) && port(ffP, \D).extract(offset, GetSize(sigP)) == sigP
 	optional
 endmatch