From: Daniel Schürmann <daniel@schuermann.dev>
Date: Sun, 19 Apr 2020 15:17:04 +0000 (+0100)
Subject: aco: use v_subrev_f32 for fsub with an sgpr operand in src1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=425558bfd595ed3a7a049ad0f47a46b8b3c4691e;p=mesa.git

aco: use v_subrev_f32 for fsub with an sgpr operand in src1

This fixes an accidentally introduced regression.

Fixes: 9be4be515f2a08b9c9e5ae1fc4c5dc9a830c2337 ('aco: implement 16-bit nir_op_fsub/nir_op_fadd')
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4633>
---

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index b4db7a0d66d..af1a5e4f111 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -1639,7 +1639,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
    }
    case nir_op_fsub: {
       Temp src0 = get_alu_src(ctx, instr->src[0]);
-      Temp src1 = as_vgpr(ctx, get_alu_src(ctx, instr->src[1]));
+      Temp src1 = get_alu_src(ctx, instr->src[1]);
       if (dst.regClass() == v2b) {
          Temp tmp = bld.tmp(v1);
          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)