From: lkcl <lkcl@web>
Date: Wed, 2 Oct 2019 09:13:14 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~3927
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=425e95c3110b993b0e1130c4c9c40b6e4e4a9d20;p=libreriscv.git

---

diff --git a/simple_v_extension/specification/bitmanip.mdwn b/simple_v_extension/specification/bitmanip.mdwn
index 23925483e..1af47e749 100644
--- a/simple_v_extension/specification/bitmanip.mdwn
+++ b/simple_v_extension/specification/bitmanip.mdwn
@@ -126,6 +126,7 @@ Pseudo-code:
 
     def sbf(rd, rs1, rs2):
         rd = 0
+        # start setting if no predicate or if 1st predicate bit set
         setting_mode = rs2 == x0 or (regs[rs2] & 1)
         while i < XLEN:
             bit = 1<<i
@@ -160,8 +161,9 @@ Pseudo-code:
 
 Pseudo-code:
 
-    def sbf(rd, rs1, rs2):
+    def sif(rd, rs1, rs2):
         rd = 0
+        # start setting if no predicate or if 1st predicate bit set
         setting_mode = rs2 == x0 or (regs[rs2] & 1)
         while i < XLEN:
             bit = 1<<i
@@ -192,3 +194,22 @@ Pseudo-code:
      1 1 0 1 0 1 0 0   a3 contents
                        sof a2, a3, a0
      0 1 x x x x 0 0   a2 contents
+
+Pseudo-code:
+
+    def sof(rd, rs1, rs2):
+        rd = 0
+        # search mode starts on
+        search_mode = True
+        while i < XLEN:
+            bit = 1<<i
+            if search_mode:
+                if regs[rs1] & bit: # found a bit in rs1:
+                    regs[rd] |= bit
+                    search_mode = False
+            else if rs2 != x0:
+                # only reenable when predicate in use, and bit valid
+                if (regs[rs2] & bit):
+                    search_mode = True # back into "search" mode
+            i += 1
+