From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 15 Feb 2022 01:35:25 +0000 (+0000)
Subject: increase size of bootmem
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4262b710c6cf7a3bc9259ac51ffe13d54803b0af;p=ls2.git

increase size of bootmem
---

diff --git a/src/ls2.py b/src/ls2.py
index 14cad43..9482112 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -82,7 +82,7 @@ class DDR3SoC(SoC, Elaboratable):
         # SRAM (but actually a ROM, for firmware), at address 0x0
         if fw_addr is not None:
             sram_width = 32
-            self.bootmem = SRAMPeripheral(size=8192, data_width=sram_width,
+            self.bootmem = SRAMPeripheral(size=0x10000, data_width=sram_width,
                                       writable=True)
             with open(firmware, "rb") as f:
                 words = iter(lambda: f.read(sram_width // 8), b'')