From: lkcl <lkcl@web>
Date: Mon, 3 Oct 2022 12:33:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~233
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=428e6f1946093cfe7ab7f34428df039f716a7b81;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn
index 8358e701f..42d1e5a61 100644
--- a/openpower/sv/svp64/discussion.mdwn
+++ b/openpower/sv/svp64/discussion.mdwn
@@ -255,7 +255,19 @@ elif immediate != 0:
 ```
 
 thus it is actually legitimate to have scalar src *and* dest especially
-with predicate masks.
+with predicate masks.  the trick noted in (4) below of setting `RA.isvec`
+would therefore activate the *Vector Indexed* mode, with associated predication-based offsets (and REMAP) which is **NOT** the same as
+`VSPLAT` mode.
+
+    elif RA.isvec:
+      # quirky Vector indexed mode but with an immediate
+      srcbase = ireg[RA+i]
+      offs = immed;
+    else
+      # standard scalar mode (but predicated)
+      # no stride multiplier means VSPLAT mode
+      srcbase = ireg[RA]
+      offs = immed
 
 ## answers to 4, loops/uses