From: lkcl <lkcl@web>
Date: Fri, 17 Jun 2022 18:38:29 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1732
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4294c3734c6f1e9d5f3039425bc44624b2376433;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 44ee7ad56..52e98cee0 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -8,6 +8,7 @@ See links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=535>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=587>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=568> TODO
+* <https://bugs.libre-soc.org/show_bug.cgi?id=862> VF Predication
 * <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
 * [[sv/svstep]]
 * pseudocode [[openpower/isa/simplev]]
@@ -176,6 +177,8 @@ because Vertical-First is not that different from executing standard
 Scalar instructions,
 a simple branch-conditional test should be used instead of predication,
 exactly as would normally be done if SVP64 was not in use.
+Alternatively the `setvl` instruction may be called again with the `vf`
+flag set. This tells the hardware to re-assess the use of Predicates
 
 These rules allow Hardware implementors to choose to
 free up the connection