From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 Feb 2021 17:47:03 +0000 (+0000)
Subject: whitespace
X-Git-Tag: LS180_RC3~190^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=42a21c50ebbcef2d7ddad1bb3da082b57a645135;p=soclayout.git

whitespace
---

diff --git a/experiments12/SPBlock_512W64B8W.v b/experiments12/SPBlock_512W64B8W.v
index 008d877..ddab968 100644
--- a/experiments12/SPBlock_512W64B8W.v
+++ b/experiments12/SPBlock_512W64B8W.v
@@ -1,3 +1,7 @@
 (* blackbox = 1 *)
-module SPBlock_512W64B8W(input [8:0] a, input [63:0] d, output [63:0] q, input [7:0] we, input clk);
+module SPBlock_512W64B8W(input [8:0] a,
+			 input [63:0] d,
+			 output [63:0] q,
+			 input [7:0] we,
+			 input clk);
 endmodule // SPBlock_512W64B8W
diff --git a/experiments12/memory.py b/experiments12/memory.py
index b540359..565d179 100644
--- a/experiments12/memory.py
+++ b/experiments12/memory.py
@@ -18,7 +18,8 @@ class ADD(Elaboratable):
         a = Signal(9)
         q = Signal(64) # output
         d = Signal(64) # input
-        sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d, i_we=self.we, i_clk=ClockSignal())
+        sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d,
+                                             i_we=self.we, i_clk=ClockSignal())
         m.submodules += sram
 
         # connect up some arbitrary signals