From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Jun 2020 04:49:20 +0000 (+0100)
Subject: code-munge
X-Git-Tag: div_pipeline~545
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=42ba93eb4cffd0509603f45bb81b9a5c2fc48183;p=soc.git

code-munge
---

diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py
index f054e3ec..9e3df2e0 100644
--- a/src/soc/fu/alu/output_stage.py
+++ b/src/soc/fu/alu/output_stage.py
@@ -20,15 +20,16 @@ class ALUOutputStage(CommonOutputStage):
         m = super().elaborate(platform)
         comb = m.d.comb
         op = self.i.ctx.op
+        xer_so_i, xer_ov_i = self.i.xer_so.data, self.i.xer_ov.data
 
         # create overflow
         ov = Signal(2, reset_less=True) # OV, OV32
 
         # XXX see https://bugs.libre-soc.org/show_bug.cgi?id=319#c5
-        comb += ov[0].eq(self.i.xer_so.data | self.i.xer_ov.data[0]) # OV
-        comb += ov[1].eq(self.i.xer_so.data | self.i.xer_ov.data[1]) # OV32 XXX!
+        comb += ov[0].eq(xer_so_i | xer_ov_i[0]) # OV
+        comb += ov[1].eq(xer_so_i | xer_ov_i[1]) # OV32 XXX!
 
-        comb += self.so.eq(self.i.xer_so.data | self.i.xer_ov.data[0]) # OV
+        comb += self.so.eq(ov[0]) # SO
 
         # copy overflow and sticky-overflow
         comb += self.o.xer_so.data.eq(self.so)