From: lkcl Date: Fri, 17 Sep 2021 17:40:09 +0000 (+0100) Subject: (no commit message) X-Git-Tag: DRAFT_SVP64_0_1~83 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=42c94ad25422f6956d8572644d08a6e051b1941a;p=libreriscv.git --- diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index e649fb73e..9246e7082 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -301,6 +301,8 @@ legitimately choose to alter srcstep and dststep in non-sequential order as part of explicit loops, it is neither possible nor safe to make speculative assumptions about future LD/STs. Therefore, Fail-First LD/ST in Vertical-First is `UNDEFINED`. +This is very different from Arithmetic (Data-dependent) FFirst +where Vertical-First Mode is deterministic, not speculative. # LOAD/STORE Elwidths