From: bugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Date: Tue, 24 Mar 2020 10:50:57 +0000 (+0000)
Subject: [libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=42cdedded86350b4db3e5d64f386d655eb2a0de0;p=libre-riscv-dev.git

[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed
---

diff --git a/f3/491ef3145ba317f3e51a962c6683e324a17900 b/f3/491ef3145ba317f3e51a962c6683e324a17900
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+Date: Tue, 24 Mar 2020 10:50:57 +0000
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+X-Bugzilla-Severity: enhancement
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+Subject: [libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or
+ partial) needed
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