From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 13 Mar 2019 07:34:56 +0000 (+0000)
Subject: whitespace
X-Git-Tag: div_pipeline~2295
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=42d2956dee15acb476007ce2ad6eda768049b430;p=soc.git

whitespace
---

diff --git a/TLB/src/TLB.py b/TLB/src/TLB.py
index ae772b55..cac8863c 100644
--- a/TLB/src/TLB.py
+++ b/TLB/src/TLB.py
@@ -40,7 +40,7 @@ class TLB():
         self.command = Signal(2) # 00=None, 01=Search, 10=Write L1, 11=Write L2
         self.xwr = Signal(3) # Execute, Write, Read
         self.mode = Signal(4) # 4 bits for access to Sv48 on Rv64
-        self.address_L1 = Signal(max= am_size)
+        self.address_L1 = Signal(max=am_size)
         self.asid = Signal(asid_size) # Address Space IDentifier (ASID)
         self.vma = Signal(vma_size) # Virtual Memory Address (VMA)
         self.pte_in = Signal(pte_size) # To be saved Page Table Entry (PTE)