From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 9 Jun 2021 13:42:41 +0000 (+0100)
Subject: add PLL clock loop-back into CPU
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=42d693196f2060bc45c929691baf583f86f19ec4;p=libresoc-litex.git

add PLL clock loop-back into CPU
---

diff --git a/libresoc/core.py b/libresoc/core.py
index 178ebe8..7ebbbdd 100644
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -186,6 +186,7 @@ class LibreSoC(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
+        self.clk          = ClockSignal()
 
         irq_en = "noirq" not in variant
 
@@ -236,7 +237,7 @@ class LibreSoC(CPU):
 
         self.cpu_params = dict(
             # Clock / Reset
-            i_clk              = ClockSignal(),
+            i_clk              = self.clk,
             i_rst              = ResetSignal() | self.reset,
 
             # Monitoring / Debugging