From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 24 Feb 2020 17:44:20 +0000 (+0000)
Subject: simplify experiment4 to an adder, similar to adder benchmark
X-Git-Tag: partial-core-ls180-gdsii~207
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=42e6798a50f2daa572b4be36968420dabfe75753;p=soclayout.git

simplify experiment4 to an adder, similar to adder benchmark
---

diff --git a/experiments4/Makefile b/experiments4/Makefile
index effb92a..8addfb5 100755
--- a/experiments4/Makefile
+++ b/experiments4/Makefile
@@ -6,7 +6,7 @@
 
            YOSYS_FLATTEN = Yes
                      CHIP = chip
-                     CORE = alu_hier
+                     CORE = add
                    MARGIN = 5
                   BOOMOPT = -A
                   BOOGOPT =
@@ -15,17 +15,17 @@
             USE_CLOCKTREE = Yes
                 USE_DEBUG = No
                  USE_KITE = No
-                 RM_CHIP = Yes
+#                 RM_CHIP = Yes
 
                  NETLISTS = $(shell cat nets.txt)
-                 PATTERNS = alu_hier_r
+                 PATTERNS = add_r
 
 
  include ./mk/design-flow.mk
 
 
-#blif:      alu_hier.blif
-#vst:       alu_hier.vst
+blif:      add.blif
+vst:       add.vst
 dreal:      dreal-chip_cts_r
 flatph:     flatph-chip_cts_r
 layout:    chip_cts_r.ap
@@ -34,4 +34,4 @@ gds:       chip_cts_r.gds
 lvx:       lvx-chip_cts_r
 druc:      druc-chip_cts_r
 view:      cgt-chip_cts_r
-sim:       asimut-alu_hier_cts_r
+sim:       asimut-add_cts_r
diff --git a/experiments4/add.py b/experiments4/add.py
new file mode 100644
index 0000000..83e7a72
--- /dev/null
+++ b/experiments4/add.py
@@ -0,0 +1,24 @@
+from nmigen import *
+from nmigen.cli import rtlil
+
+
+class ADD(Elaboratable):
+    def __init__(self, width):
+        self.a   = Signal(width)
+        self.b   = Signal(width)
+        self.o   = Signal(width)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.comb += self.eq(self.a + self.b)
+        return m
+
+
+def create_ilang(dut, ports, test_name):
+    vl = rtlil.convert(dut, name=test_name, ports=ports)
+    with open("%s.il" % test_name, "w") as f:
+        f.write(vl)
+
+if __name__ == "__main__":
+    alu = ADD(width=4)
+    create_ilang(alu, [alu.a, alu.b, alu.o], "add")
diff --git a/experiments4/alu_hier.py b/experiments4/alu_hier.py
deleted file mode 100644
index b42fb1d..0000000
--- a/experiments4/alu_hier.py
+++ /dev/null
@@ -1,68 +0,0 @@
-from nmigen import *
-from nmigen.cli import rtlil
-
-
-class Adder(Elaboratable):
-    def __init__(self, width):
-        self.a   = Signal(width)
-        self.b   = Signal(width)
-        self.o   = Signal(width)
-
-    def elaborate(self, platform):
-        m = Module()
-        m.d.comb += self.o.eq(self.a + self.b)
-        return m
-
-
-class Subtractor(Elaboratable):
-    def __init__(self, width):
-        self.a   = Signal(width)
-        self.b   = Signal(width)
-        self.o   = Signal(width)
-
-    def elaborate(self, platform):
-        m = Module()
-        m.d.comb += self.o.eq(self.a - self.b)
-        return m
-
-
-class ALU(Elaboratable):
-    def __init__(self, width):
-        self.op  = Signal()
-        self.a   = Signal(width)
-        self.b   = Signal(width)
-        self.o   = Signal(width)
-
-        self.add = Adder(width)
-        self.sub = Subtractor(width)
-
-    def elaborate(self, platform):
-
-        m = Module()
-        #m.domains.sync = ClockDomain()
-        #m.d.comb += ClockSignal().eq(self.m_clock)
-
-        m.submodules.add = self.add
-        m.submodules.sub = self.sub
-        m.d.comb += [
-            self.add.a.eq(self.a),
-            self.sub.a.eq(self.a),
-            self.add.b.eq(self.b),
-            self.sub.b.eq(self.b),
-        ]
-        with m.If(self.op):
-            m.d.sync += self.o.eq(self.sub.o)
-        with m.Else():
-            m.d.sync += self.o.eq(self.add.o)
-        return m
-
-
-def create_ilang(dut, ports, test_name):
-    vl = rtlil.convert(dut, name=test_name, ports=ports)
-    with open("%s.il" % test_name, "w") as f:
-        f.write(vl)
-
-if __name__ == "__main__":
-    alu = ALU(width=16)
-    create_ilang(alu, [#alu.m_clock, alu.p_reset,
-                       alu.op, alu.a, alu.b, alu.o], "alu_hier")
diff --git a/experiments4/nets.txt b/experiments4/nets.txt
index 320e403..76d4bb8 100644
--- a/experiments4/nets.txt
+++ b/experiments4/nets.txt
@@ -1 +1 @@
-alu_hier add sub
+add