From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Tue, 26 Sep 2023 10:29:47 +0000 (+0100)
Subject: Added brackets for lhaux instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=42e72ffae4f732c69aea4e05136a7aa326a8ba6c;p=openpower-isa.git

Added brackets for lhaux instruction
---

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 16575ce5..1199024d 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -307,7 +307,7 @@ Description:
 
     Let the effective address (EA) be the sum (RA)+ (RB).
     The halfword in storage addressed by EA is loaded into
-    RT48:63. RT 0:47 are filled with a copy of bit 0 of the
+    RT[48:63]. RT[0:47] are filled with a copy of bit 0 of the
     loaded halfword.
 
     EA is placed into register RA.