From: Luke Kenneth Casson Leighton Date: Wed, 29 Mar 2023 21:29:22 +0000 (+0100) Subject: clarify section for regfiles X-Git-Tag: opf_rfc_ls012_v1~227 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=42efba984d8021f1eae4d13ed299f0295146389e;p=libreriscv.git clarify section for regfiles --- diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index 319ff875c..6db9dcf5b 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -121,10 +121,12 @@ register-register operations. To be absolutely clear: -**No conceptual arithmetic ordering or other changes over the Scalar Power ISA -definitions to registers or register files -or to arithmetic or Logical Operations beyond element-width subdivision and -sequential element numbering are expressed or implied** +``` + No conceptual arithmetic ordering or other changes over the Scalar + Power ISA definitions to registers or register files or to arithmetic + or Logical Operations beyond element-width subdivision and sequential + element numbering are expressed or implied +``` Whilst the bits within the GPRs and FPRs are expected to be MSB0-ordered and for numbering to be sequentially incremental the element offset