From: Kevin Lim <ktlim@umich.edu>
Date: Wed, 12 Jan 2005 00:00:16 +0000 (-0500)
Subject: Merge changes.
X-Git-Tag: m5_1.0_tutorial~76^2~9
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=42f3b4ffb3fedcb70e9ff068ed7160dc6020b8c4;p=gem5.git

Merge changes.

base/traceflags.py:
    Merge extra new CPU flags
cpu/static_inst.hh:
    Include all the execute functions in static_inst_impl.hh

--HG--
extra : convert_revision : 78eb753bf709d37400e7c2418bb35d842d7c3f63
---

42f3b4ffb3fedcb70e9ff068ed7160dc6020b8c4
diff --cc SConscript
index f6c472216,8a9b99cb5..9d3a41964
--- a/SConscript
+++ b/SConscript
@@@ -44,9 -44,9 +44,10 @@@ Import('env'
  # Base sources used by all configurations.
  base_sources = Split('''
  	arch/alpha/decoder.cc
+         arch/alpha/alpha_full_cpu_exec.cc
  	arch/alpha/fast_cpu_exec.cc
  	arch/alpha/simple_cpu_exec.cc
 +	arch/alpha/inorder_cpu_exec.cc
  	arch/alpha/full_cpu_exec.cc
  	arch/alpha/faults.cc
  	arch/alpha/isa_traits.cc
@@@ -442,9 -418,9 +465,10 @@@ env.Command(Split('base/traceflags.hh b
  # several files are generated from arch/$TARGET_ISA/isa_desc.
  env.Command(Split('''arch/alpha/decoder.cc
  		     arch/alpha/decoder.hh
+                      arch/alpha/alpha_full_cpu_exec.cc
  		     arch/alpha/fast_cpu_exec.cc
                       arch/alpha/simple_cpu_exec.cc
 +                     arch/alpha/inorder_cpu_exec.cc
                       arch/alpha/full_cpu_exec.cc'''),
              Split('''arch/alpha/isa_desc
  		     arch/isa_parser.py'''),
diff --cc base/traceflags.py
index 8f20a9692,eb404fa54..1f69e5e88
--- a/base/traceflags.py
+++ b/base/traceflags.py
@@@ -123,7 -123,21 +123,22 @@@ baseFlags = 
      'Uart',
      'Split',
      'SQL',
-     'Thread'
++    'Thread',
+     'Fetch',
+     'Decode',
+     'Rename',
+     'IEW',
+     'Commit',
+     'IQ',
+     'ROB',
+     'FreeList',
+     'RenameMap',
+     'LDSTQ',
+     'StoreSet',
+     'MemDepUnit',
+     'DynInst',
+     'FullCPU',
+     'CommitRate'
      ]
  
  #
diff --cc cpu/base_cpu.cc
index 7605ff3c3,988c7a602..2275f12e3
--- a/cpu/base_cpu.cc
+++ b/cpu/base_cpu.cc
@@@ -47,8 -48,9 +49,9 @@@ vector<BaseCPU *> BaseCPU::cpuList
  // been initialized
  int maxThreadsPerCPU = 1;
  
+ extern void debug_break();
  #ifdef FULL_SYSTEM
 -BaseCPU::BaseCPU(const string &_name, int _number_of_threads,
 +BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg,
                   Counter max_insts_any_thread,
                   Counter max_insts_all_threads,
                   Counter max_loads_any_thread,
@@@ -63,12 -63,14 +66,16 @@@ BaseCPU::BaseCPU(const string &_name, i
                   Counter max_insts_any_thread,
                   Counter max_insts_all_threads,
                   Counter max_loads_any_thread,
 -                 Counter max_loads_all_threads)
 -    : SimObject(_name), number_of_threads(_number_of_threads)
 +                 Counter max_loads_all_threads,
 +                 bool _function_trace, Tick _function_trace_start)
 +    : SimObject(_name), deferRegistration(_def_reg),
 +      number_of_threads(_number_of_threads)
  #endif
  {
+     DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this);
+ 
+     debug_break();
+ 
      // add self to global list of CPUs
      cpuList.push_back(this);
  
diff --cc cpu/static_inst.hh
index 46b2e4b19,71e9ef441..c47fa32db
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@@ -40,11 -40,14 +40,15 @@@
  #include "targetarch/isa_traits.hh"
  
  // forward declarations
+ struct AlphaSimpleImpl;
  class ExecContext;
  class DynInst;
+ template <class Impl>
+ class AlphaDynInst;
+ 
  class FastCPU;
  class SimpleCPU;
 +class InorderCPU;
  class SymbolTable;
  
  namespace Trace {