From: Luke Kenneth Casson Leighton Date: Thu, 22 Dec 2022 17:47:07 +0000 (+0000) Subject: reduce number of lines X-Git-Tag: opf_rfc_ls005_v1~10 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=430ccaa2e6a8689ef0ec756ed737b7f1a2cf1603;p=libreriscv.git reduce number of lines --- diff --git a/openpower/sv/rfc/ls005.mdwn b/openpower/sv/rfc/ls005.mdwn index fd6635cd6..f449ff4f9 100644 --- a/openpower/sv/rfc/ls005.mdwn +++ b/openpower/sv/rfc/ls005.mdwn @@ -30,12 +30,10 @@ **Summary** ``` - Exactly as is already done in RISC-V, convert the entire - use of 64-bit hard-coding to "XLEN". Exactly as is in RISC-V, - options then include PowerISA-32, PowerISA-64 and PowerISA-128. - Unlike in RISC-V, the concept of PowerISA-16 and PowerISA-8 is - also floated, for Embedded, AI, Edge, Processing-in-Memory, - Distributed Computing and other purposes. + Exactly as is already done in RISC-V, convert the entire use of 64-bit hard-coding to "XLEN". + Exactly as is in RISC-V, options then include PowerISA-32, PowerISA-64 and PowerISA-128. + Unlike in RISC-V, the concept of PowerISA-16 and PowerISA-8 is also floated, for Embedded, + AI, Edge, Processing-in-Memory, Distributed Computing and other purposes. ``` **Submitter**: Luke Leighton (Libre-SOC)