From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 24 Sep 2022 13:25:09 +0000 (+0100)
Subject: add extra test_pysvp64dis.py test for ff=~RC1/vli mode
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=433665cc8903284c91cf151b134795009b4dd212;p=openpower-isa.git

add extra test_pysvp64dis.py test for ff=~RC1/vli mode
---

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index cea9113c..9f5dd88a 100644
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -284,6 +284,7 @@ class SVSTATETestCase(unittest.TestCase):
     def test_17_vli(self):
         expected = [
                     "sv.add/ff=RC1/vli 3,7,11",
+                    "sv.add/ff=~RC1/vli 3,7,11",
                         ]
         self._do_tst(expected)