From: lkcl <lkcl@web>
Date: Fri, 6 May 2022 08:10:21 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2406
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=435a46e06d67e46fc2fb64d09b1c78f9d34e0527;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 727e2d9f6..60d02997a 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -325,8 +325,10 @@ left anaemic.
 
 A particular key instruction that is missing is `MV.X` which is
 illustrated as `GPR(dest) = GPR(GPR(src))`. This horrendously
-expensive instruction is almost never added to a Scalar ISA but
-is almost always added to a Vector one, it allows for arbitrary
+expensive instruction causing a huge swathe of Register Hazards
+in one single hit is almost never added to a Scalar ISA but
+is almost always added to a Vector one. When `MV.X` is
+Vectorised it allows for arbitrary
 remapping of elements within a Vector to positions specified
 by another Vector. A typical Scalar ISA will use Memory to
 achieve this task, but with Vector ISAs the Vector Register Files are