From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sun, 10 May 2020 22:52:45 +0000 (-0400)
Subject: Implement rlwimi as well
X-Git-Tag: div_pipeline~1295
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4366db6185513d97b1f9af0b27f42d4a28a9e08f;p=soc.git

Implement rlwimi as well
---

diff --git a/src/soc/alu/input_stage.py b/src/soc/alu/input_stage.py
index ed86a5bf..389954b5 100644
--- a/src/soc/alu/input_stage.py
+++ b/src/soc/alu/input_stage.py
@@ -5,6 +5,7 @@
 from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed,
                     unsigned)
 from nmutil.pipemodbase import PipeModBase
+from soc.decoder.power_enums import InternalOp
 from soc.alu.pipe_data import ALUInputData
 from soc.decoder.power_enums import CryIn
 
@@ -38,7 +39,8 @@ class ALUInputStage(PipeModBase):
         ##### operand B #####
 
         # If there's an immediate, set the B operand to that
-        with m.If(self.i.ctx.op.imm_data.imm_ok):
+        with m.If(self.i.ctx.op.imm_data.imm_ok &
+                  ~(self.i.ctx.op.insn_type == InternalOp.OP_RLC)):
             comb += self.o.b.eq(self.i.ctx.op.imm_data.imm)
         with m.Else():
             comb += self.o.b.eq(self.i.b)
diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index 173ca78f..59c896a5 100644
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -134,7 +134,10 @@ class ALUMainStage(PipeModBase):
                     comb += self.o.o.eq(rotl_out & mask)
 
             with m.Case(InternalOp.OP_RLC):
-                comb += rotate_amt.eq(self.i.b[0:5])
+                with m.If(self.i.ctx.op.imm_data.imm_ok):
+                    comb += rotate_amt.eq(self.i.ctx.op.imm_data.imm[0:5])
+                with m.Else():
+                    comb += rotate_amt.eq(self.i.b[0:5])
                 comb += maskgen.mb.eq(mb+32)
                 comb += maskgen.me.eq(me+32)
                 comb += mask.eq(maskgen.o)
diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index 04363ab8..bf5a7e24 100644
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -157,6 +157,15 @@ class ALUTestCase(FHDLTestCase):
             with Program(lst) as program:
                 sim = self.run_tst_program(program, initial_regs)
 
+    def test_rlwimi(self):
+        lst = ["rlwinm 3, 1, 5, 20, 6",
+               "rlwimi 3, 1, 5, 20, 6"]
+        initial_regs = [0] * 32
+        initial_regs[1] = random.randint(0, (1<<64)-1)
+        initial_regs[3] = random.randint(0, (1<<64)-1)
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+
     def test_ilang(self):
         rec = CompALUOpSubset()
 
diff --git a/src/soc/decoder/isa/fixedshift.patch b/src/soc/decoder/isa/fixedshift.patch
index b9f8908a..8485cd8c 100644
--- a/src/soc/decoder/isa/fixedshift.patch
+++ b/src/soc/decoder/isa/fixedshift.patch
@@ -1,6 +1,6 @@
 --- fixedshift.py.orig	2020-05-09 09:56:10.393656481 -0400
-+++ fixedshift.py	2020-05-10 16:03:17.449405581 -0400
-@@ -12,8 +12,8 @@
++++ fixedshift.py	2020-05-10 18:51:24.725396454 -0400
+@@ -12,48 +12,48 @@
      @inject()
      def op_rlwinm(self, RS):
          n = SH
@@ -11,47 +11,52 @@
          RA = r & m
          return (RA,)
  
-@@ -21,7 +21,7 @@
+     @inject()
      def op_rlwinm_(self, RS):
          n = SH
-         r = ROTL32(RS[32:64], n)
+-        r = ROTL32(RS[32:64], n)
 -        m = MASK(MB + 32, ME + 32)
++        r = ROTL32(EXTZ64(RS[32:64]), n)
 +        m = MASK(MB.value + 32, ME.value + 32)
          RA = r & m
          return (RA,)
  
-@@ -29,7 +29,7 @@
+     @inject()
      def op_rlwnm(self, RB, RS):
          n = RB[59:64]
-         r = ROTL32(RS[32:64], n)
+-        r = ROTL32(RS[32:64], n)
 -        m = MASK(MB + 32, ME + 32)
++        r = ROTL32(EXTZ64(RS[32:64]), n)
 +        m = MASK(MB.value + 32, ME.value + 32)
          RA = r & m
          return (RA,)
  
-@@ -37,7 +37,7 @@
+     @inject()
      def op_rlwnm_(self, RB, RS):
          n = RB[59:64]
-         r = ROTL32(RS[32:64], n)
+-        r = ROTL32(RS[32:64], n)
 -        m = MASK(MB + 32, ME + 32)
++        r = ROTL32(EXTZ64(RS[32:64]), n)
 +        m = MASK(MB.value + 32, ME.value + 32)
          RA = r & m
          return (RA,)
  
-@@ -45,7 +45,7 @@
+     @inject()
      def op_rlwimi(self, RS, RA):
          n = SH
-         r = ROTL32(RS[32:64], n)
+-        r = ROTL32(RS[32:64], n)
 -        m = MASK(MB + 32, ME + 32)
++        r = ROTL32(EXTZ64(RS[32:64]), n)
 +        m = MASK(MB.value + 32, ME.value + 32)
          RA = r & m | RA & ~m
          return (RA,)
  
-@@ -53,7 +53,7 @@
+     @inject()
      def op_rlwimi_(self, RS, RA):
          n = SH
-         r = ROTL32(RS[32:64], n)
+-        r = ROTL32(RS[32:64], n)
 -        m = MASK(MB + 32, ME + 32)
++        r = ROTL32(EXTZ64(RS[32:64]), n)
 +        m = MASK(MB.value + 32, ME.value + 32)
          RA = r & m | RA & ~m
          return (RA,)