From: Kristian H. Kristensen <hoegsberg@google.com>
Date: Thu, 10 Oct 2019 22:09:49 +0000 (-0700)
Subject: freedreno/ir3: Add new LDLW/STLW instructions
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=436d125adfab09d2c31835fc9dca49c308039c06;p=mesa.git

freedreno/ir3: Add new LDLW/STLW instructions

These access memory used for passing data between geometry stages.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
---

diff --git a/src/freedreno/ir3/ir3.c b/src/freedreno/ir3/ir3.c
index 72809c4a548..aaf33bc6de2 100644
--- a/src/freedreno/ir3/ir3.c
+++ b/src/freedreno/ir3/ir3.c
@@ -793,7 +793,7 @@ static int emit_cat6(struct ir3_instruction *instr, void *ptr,
 
 		return 0;
 	} else if (instr->cat6.src_offset || (instr->opc == OPC_LDG) ||
-			(instr->opc == OPC_LDL)) {
+			(instr->opc == OPC_LDL) || (instr->opc == OPC_LDLW)) {
 		struct ir3_register *src3 = instr->regs[3];
 		instr_cat6a_t *cat6a = ptr;
 
@@ -823,7 +823,7 @@ static int emit_cat6(struct ir3_instruction *instr, void *ptr,
 	}
 
 	if (instr->cat6.dst_offset || (instr->opc == OPC_STG) ||
-			(instr->opc == OPC_STL)) {
+			(instr->opc == OPC_STL) || (instr->opc == OPC_STLW)) {
 		instr_cat6c_t *cat6c = ptr;
 		cat6->dst_off = true;
 		cat6c->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF);
diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h
index cf53fa087d3..34447c2cc2b 100644
--- a/src/freedreno/ir3/ir3.h
+++ b/src/freedreno/ir3/ir3.h
@@ -1409,8 +1409,10 @@ ir3_SAM(struct ir3_block *block, opc_t opc, type_t type,
 INSTR2(LDLV)
 INSTR3(LDG)
 INSTR3(LDL)
+INSTR3(LDLW)
 INSTR3(STG)
 INSTR3(STL)
+INSTR3(STLW)
 INSTR1(RESINFO)
 INSTR1(RESFMT)
 INSTR2(ATOMIC_ADD)
diff --git a/src/freedreno/ir3/ir3_cp.c b/src/freedreno/ir3/ir3_cp.c
index 704ddf99937..d60c1aae49c 100644
--- a/src/freedreno/ir3/ir3_cp.c
+++ b/src/freedreno/ir3/ir3_cp.c
@@ -216,6 +216,9 @@ static bool valid_flags(struct ir3_instruction *instr, unsigned n,
 			if ((instr->opc == OPC_STL) && (n != 2))
 				return false;
 
+			if (instr->opc == OPC_STLW && n == 0)
+				return false;
+
 			/* disallow CP into anything but the SSBO slot argument for
 			 * atomics:
 			 */
diff --git a/src/freedreno/ir3/ir3_legalize.c b/src/freedreno/ir3/ir3_legalize.c
index 5a866abf178..1af80367e50 100644
--- a/src/freedreno/ir3/ir3_legalize.c
+++ b/src/freedreno/ir3/ir3_legalize.c
@@ -248,7 +248,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
 			/* seems like ldlv needs (ss) bit instead??  which is odd but
 			 * makes a bunch of flat-varying tests start working on a4xx.
 			 */
-			if ((n->opc == OPC_LDLV) || (n->opc == OPC_LDL))
+			if ((n->opc == OPC_LDLV) || (n->opc == OPC_LDL) || (n->opc == OPC_LDLW))
 				regmask_set(&state->needs_ss, n->regs[0]);
 			else
 				regmask_set(&state->needs_sy, n->regs[0]);