From: Nick Clifton Date: Fri, 1 Dec 2000 20:05:32 +0000 (+0000) Subject: Improve MIPS32 support X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4372b673222291cc81879e291c0233c6cc08a4d3;p=binutils-gdb.git Improve MIPS32 support --- diff --git a/gas/ChangeLog b/gas/ChangeLog index caed5bc850a..9c8a3df0be3 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -4,6 +4,15 @@ don't accept as constant the difference between the addresses of symbols in two different sections. + * config/tc-mips.c (macro_build): Add new 'U' and 'J' operand + specifiers. + (validate_mips_insn): Likewise. Also, update 'B' operand + specifier to use OP_*_CODE20 constants and delete 'm' operand + specifier. + (mips_ip): Remove 'm' operand specifier, add 'U' and 'J' + operand specifiers. Change warning generated by 'B' operand + specifier to reflect its new multi-purpose usage. + 2000-12-01 Joel Sherrill * configure.in (arm-*-rtems*, a29k-*rtems*, h8300-*-rtems*): diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index ef6304dbb8e..568d2615fe7 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -2597,6 +2597,15 @@ macro_build (place, counter, ep, name, fmt, va_alist) insn.insn_opcode |= va_arg (args, int) << 11; continue; + case 'U': + { + int tmp = va_arg (args, int); + + insn.insn_opcode |= tmp << 16; + insn.insn_opcode |= tmp << 11; + continue; + } + case 'V': case 'S': insn.insn_opcode |= va_arg (args, int) << 11; @@ -2617,6 +2626,10 @@ macro_build (place, counter, ep, name, fmt, va_alist) insn.insn_opcode |= va_arg (args, int) << 6; continue; + case 'J': + insn.insn_opcode |= va_arg (args, int) << 6; + continue; + case 'q': insn.insn_opcode |= va_arg (args, int) << 6; continue; @@ -6976,7 +6989,7 @@ validate_mips_insn (opc) case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; case 'A': break; - case 'B': USE_BITS (OP_MASK_SYSCALL, OP_SH_SYSCALL); break; + case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; @@ -6984,6 +6997,7 @@ validate_mips_insn (opc) case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; case 'I': break; + case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; case 'L': break; case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; @@ -7002,7 +7016,6 @@ validate_mips_insn (opc) case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; case 'l': break; - case 'm': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; @@ -7015,6 +7028,8 @@ validate_mips_insn (opc) case 'x': break; case 'z': break; case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; + case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); + USE_BITS (OP_MASK_RT, OP_SH_RT); break; default: as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), c, opc->name, opc->args); @@ -7268,29 +7283,11 @@ mips_ip (str, ip) s = expr_end; continue; - case 'm': /* Full 20 bit break code. */ + case 'B': /* 20-bit syscall/break code. */ my_getExpression (&imm_expr, s); - check_absolute_expr (ip, &imm_expr); - if ((unsigned) imm_expr.X_add_number > 0xfffff) - { - as_warn (_("Illegal break code (%ld)"), - (long) imm_expr.X_add_number); - imm_expr.X_add_number &= 0xfffff; - } - - ip->insn_opcode |= imm_expr.X_add_number << 6; - imm_expr.X_op = O_absent; - s = expr_end; - - continue; - - case 'B': /* syscall code */ - my_getExpression (&imm_expr, s); - check_absolute_expr (ip, &imm_expr); - if ((unsigned) imm_expr.X_add_number > 0xfffff) - as_warn (_("Illegal syscall code (%ld)"), + as_warn (_("Illegal 20-bit code (%ld)"), (long) imm_expr.X_add_number); ip->insn_opcode |= imm_expr.X_add_number << 6; imm_expr.X_op = O_absent; @@ -7311,6 +7308,17 @@ mips_ip (str, ip) s = expr_end; continue; + case 'J': /* 19-bit wait code. */ + my_getExpression (&imm_expr, s); + check_absolute_expr (ip, &imm_expr); + if ((unsigned) imm_expr.X_add_number > 0x7ffff) + as_warn (_("Illegal 19-bit code (%ld)"), + (long) imm_expr.X_add_number); + ip->insn_opcode |= imm_expr.X_add_number << 6; + imm_expr.X_op = O_absent; + s = expr_end; + continue; + case 'P': /* Performance register */ my_getExpression (&imm_expr, s); check_absolute_expr (ip, &imm_expr); @@ -7336,6 +7344,7 @@ mips_ip (str, ip) case 'G': /* coprocessor destination register */ case 'x': /* ignore register name */ case 'z': /* must be zero register */ + case 'U': /* destination register (clo/clz). */ s_reset = s; if (s[0] == '$') { @@ -7450,6 +7459,10 @@ mips_ip (str, ip) case 'G': ip->insn_opcode |= regno << 11; break; + case 'U': + ip->insn_opcode |= regno << 11; + ip->insn_opcode |= regno << 16; + break; case 'w': case 't': case 'E': diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 32e2baf0c38..902544a76ee 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,13 @@ +2000-12-01 Chris Demetriou + + mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete. + (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old + OP_*_SYSCALL definitions. + (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as + 19 bit wait codes. + (MIPS operand specifier comments): Remove 'm', add 'U' and + 'J', and update the meaning of 'B' so that it's more general. + 2000-10-20 Jakub Jelinek * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 95415e0c30e..61931f6c012 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -48,9 +48,11 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * breakpoint instruction are not defined; Kane says the breakpoint code field in BREAK is 20 bits; yet MIPS assemblers and debuggers only use ten bits). An optional two-operand form of break/sdbbp - allows the lower ten bits to be set too. + allows the lower ten bits to be set too, and MIPS32 and later + architectures allow 20 bits to be set with a signal operand + (using CODE20). - The syscall instruction uses SYSCALL. + The syscall instruction uses CODE20. The general coprocessor instructions use COPZ. */ @@ -82,8 +84,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define OP_SH_PREFX 11 #define OP_MASK_CCC 0x7 #define OP_SH_CCC 8 -#define OP_MASK_SYSCALL 0xfffff -#define OP_SH_SYSCALL 6 +#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ +#define OP_SH_CODE20 6 #define OP_MASK_SHAMT 0x1f #define OP_SH_SHAMT 6 #define OP_MASK_FD 0x1f @@ -100,17 +102,17 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define OP_SH_FUNCT 0 #define OP_MASK_SPEC 0x3f #define OP_SH_SPEC 0 -#define OP_SH_LOCC 8 /* FP condition code */ -#define OP_SH_HICC 18 /* FP condition code */ +#define OP_SH_LOCC 8 /* FP condition code. */ +#define OP_SH_HICC 18 /* FP condition code. */ #define OP_MASK_CC 0x7 -#define OP_SH_COP1NORM 25 /* Normal COP1 encoding */ -#define OP_MASK_COP1NORM 0x1 /* a single bit */ -#define OP_SH_COP1SPEC 21 /* COP1 encodings */ +#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ +#define OP_MASK_COP1NORM 0x1 /* a single bit. */ +#define OP_SH_COP1SPEC 21 /* COP1 encodings. */ #define OP_MASK_COP1SPEC 0xf #define OP_MASK_COP1SCLR 0x4 #define OP_MASK_COP1CMP 0x3 #define OP_SH_COP1CMP 4 -#define OP_SH_FORMAT 21 /* FP short format field */ +#define OP_SH_FORMAT 21 /* FP short format field. */ #define OP_MASK_FORMAT 0x7 #define OP_SH_TRUE 16 #define OP_MASK_TRUE 0x1 @@ -120,16 +122,17 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define OP_MASK_UNSIGNED 0x1 #define OP_SH_HINT 16 #define OP_MASK_HINT 0x1f -#define OP_SH_MMI 0 /* Multimedia (parallel) op */ +#define OP_SH_MMI 0 /* Multimedia (parallel) op. */ #define OP_MASK_MMI 0x3f #define OP_SH_MMISUB 6 #define OP_MASK_MMISUB 0x1f -#define OP_MASK_PERFREG 0x1f /* Performance monitoring */ +#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ #define OP_SH_PERFREG 1 -#define OP_SH_SEL 0 /* Coprocessor select field */ -#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ -#define OP_SH_CODE20 6 /* 20 bit breakpoint code */ -#define OP_MASK_CODE20 0xfffff +#define OP_SH_SEL 0 /* Coprocessor select field. */ +#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ +#define OP_SH_CODE19 6 /* 19 bit wait code. */ +#define OP_MASK_CODE19 0x7ffff + /* This structure holds information for a particular instruction. */ @@ -176,7 +179,6 @@ struct mips_opcode "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) "j" 16 bit signed immediate (OP_*_DELTA) "k" 5 bit cache opcode in target register position (OP_*_CACHE) - "m" 20 bit breakpoint code (OP_*_CODE20) "o" 16 bit signed offset (OP_*_DELTA) "p" 16 bit PC relative branch target address (OP_*_DELTA) "q" 10 bit extra breakpoint code (OP_*_CODE2) @@ -186,8 +188,11 @@ struct mips_opcode "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) "v" 5 bit same register used as both source and destination (OP_*_RS) "w" 5 bit same register used as both target and destination (OP_*_RT) + "U" 5 bit same destination register in both OP_*_RD and OP_*_RT + (used by clo and clz) "C" 25 bit coprocessor function code (OP_*_COPZ) - "B" 20 bit syscall function code (OP_*_SYSCALL) + "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) + "J" 19 bit wait function code (OP_*_CODE19) "x" accept and ignore register name "z" must be zero register @@ -221,8 +226,8 @@ struct mips_opcode Characters used so far, for quick reference when adding more: "<>()," - "ABCDEFGHILMNPSTRVW" - "abcdfhijklmopqrstuvwxz" + "ABCDEFGHIJLMNPRSTUVW" + "abcdfhijklopqrstuvwxz" */ /* These are the bits which may be set in the pinfo field of an diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ba54c74bbbe..debb7fb7e51 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,17 @@ +2000-12-01 Chris Demetriou + + mips-dis.c (print_insn_arg): Handle new 'U' and 'J' argument + specifiers. Update 'B' for new constant names, and remove + 'm'. + mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop" + near the top of the array, so they are disassembled properly. + Enable "ssnop" for MIPS32. Add "break" variant with 20 bit + code for MIPS32. Update "clo" and "clz" to use 'U' operand + specifier. Add 'H' format specifier variants for "mfc1," + "mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32. Update + MIPS32 "sdbbp" to use 'B' operand specifier. Add MIPS32 + "wait" variant which uses 'J' operand specifier. + 2000-11-28 Hans-Peter Nilsson * sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned. diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 4c76cde4aae..39bcf336c71 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -157,6 +157,30 @@ print_insn_arg (d, l, pc, info) reg_names[(l >> OP_SH_RD) & OP_MASK_RD]); break; + case 'U': + { + /* First check for both rd and rt being equal. */ + int reg = (l >> OP_SH_RD) & OP_MASK_RD; + if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) + (*info->fprintf_func) (info->stream, "$%s", + reg_names[reg]); + else + { + /* If one is zero use the other. */ + if (reg == 0) + (*info->fprintf_func) (info->stream, "$%s", + reg_names[(l >> OP_SH_RT) & OP_MASK_RT]); + else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) + (*info->fprintf_func) (info->stream, "$%s", + reg_names[reg]); + else /* Bogus, result depends on processor. */ + (*info->fprintf_func) (info->stream, "$%s or $%s", + reg_names[reg], + reg_names[(l >> OP_SH_RT) & OP_MASK_RT]); + } + } + break; + case 'z': (*info->fprintf_func) (info->stream, "$%s", reg_names[0]); break; @@ -171,17 +195,11 @@ print_insn_arg (d, l, pc, info) (l >> OP_SH_CODE) & OP_MASK_CODE); break; - case 'q': (*info->fprintf_func) (info->stream, "0x%x", (l >> OP_SH_CODE2) & OP_MASK_CODE2); break; - case 'm': - (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_CODE20) & OP_MASK_CODE20); - break; - case 'C': (*info->fprintf_func) (info->stream, "0x%x", (l >> OP_SH_COPZ) & OP_MASK_COPZ); @@ -189,7 +207,12 @@ print_insn_arg (d, l, pc, info) case 'B': (*info->fprintf_func) (info->stream, "0x%x", - (l >> OP_SH_SYSCALL) & OP_MASK_SYSCALL); + (l >> OP_SH_CODE20) & OP_MASK_CODE20); + break; + + case 'J': + (*info->fprintf_func) (info->stream, "0x%x", + (l >> OP_SH_CODE19) & OP_MASK_CODE19); break; case 'S': @@ -198,7 +221,6 @@ print_insn_arg (d, l, pc, info) (l >> OP_SH_FS) & OP_MASK_FS); break; - case 'T': case 'W': (*info->fprintf_func) (info->stream, "$f%d", diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 1c2a249d23c..3e19ffa2f5d 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -107,12 +107,15 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * Many instructions are short hand for other instructions (i.e., The jal instruction is short for jalr ). */ -const struct mips_opcode mips_builtin_opcodes[] = { +const struct mips_opcode mips_builtin_opcodes[] = +{ /* These instructions appear first so that the disassembler will find them first. The assemblers uses a hash table based on the instruction name anyhow. */ /* name, args, match, mask, pinfo, membership */ -{"nop", "", 0x00000000, 0xffffffff, 0, I1 }, +{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1|P4}, +{"nop", "", 0x00000000, 0xffffffff, 0, I1 }, +{"ssnop", "", 0x00000040, 0xffffffff, 0, M1|P4 }, {"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */ {"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */ {"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 }, @@ -220,6 +223,7 @@ const struct mips_opcode mips_builtin_opcodes[] = { {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2 }, {"break", "", 0x0000000d, 0xffffffff, TRAP, I1 }, +{"break", "B", 0x0000000d, 0xfc00003f, TRAP, P4 }, {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 }, {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 }, {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, @@ -328,8 +332,8 @@ const struct mips_opcode mips_builtin_opcodes[] = { {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 }, {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, -{"clo", "d,s", 0x70000021, 0xfc1f07ff, WR_d|RD_s, P4 }, -{"clz", "d,s", 0x70000020, 0xfc1f07ff, WR_d|RD_s, P4 }, +{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|RD_s, P4 }, +{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|RD_s, P4 }, {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 }, {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 }, @@ -545,8 +549,11 @@ const struct mips_opcode mips_builtin_opcodes[] = { {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, P4 }, {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1}, {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1}, +{"mfc1", "t,G,H", 0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S, P4}, {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, +{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, P4 }, {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, +{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, P4 }, {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 }, {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 }, {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 }, @@ -580,8 +587,11 @@ const struct mips_opcode mips_builtin_opcodes[] = { {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, P4 }, {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, +{"mtc1", "t,G,H", 0x44800000, 0xffe007f8, COD|RD_t|WR_S|FP_S, P4 }, {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 }, +{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, P4 }, {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 }, +{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, P4 }, {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 }, {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 }, {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, @@ -620,7 +630,7 @@ const struct mips_opcode mips_builtin_opcodes[] = { {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5}, {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5}, -{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1|P4 }, +/* pref is at the start of the table. */ {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 }, {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5}, @@ -657,7 +667,7 @@ const struct mips_opcode mips_builtin_opcodes[] = { {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2|M1 }, {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2|M1 }, {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2|M1 }, -{"sdbbp", "m", 0x7000003f, 0xfc00003f, TRAP, P4 }, +{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, P4 }, {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 }, {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 }, @@ -711,7 +721,7 @@ const struct mips_opcode mips_builtin_opcodes[] = { {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */ {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 }, -{"ssnop", "", 0x00000040, 0xffffffff, 0, M1 }, +/* ssnop is at the start of the table. */ {"standby", "", 0x42000021, 0xffffffff, 0, V1 }, {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 }, @@ -810,6 +820,7 @@ const struct mips_opcode mips_builtin_opcodes[] = { {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 }, {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 }, {"wait", "", 0x42000020, 0xffffffff, TRAP, I3|M1|P4 }, +{"wait", "J", 0x42000020, 0xfe00003f, TRAP, P4 }, {"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 }, {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 }, /* No hazard protection on coprocessor instructions--they shouldn't