From: Megan Wachs Date: Wed, 6 Sep 2017 01:40:22 +0000 (-0700) Subject: i2c/uart: Name the synchronizers X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4381e395af0fcc2dafc5d10556978040c7a175ea;p=sifive-blocks.git i2c/uart: Name the synchronizers --- diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala index 2e29423..9bbc576 100644 --- a/src/main/scala/devices/i2c/I2CPins.scala +++ b/src/main/scala/devices/i2c/I2CPins.scala @@ -18,11 +18,13 @@ class I2CPins[T <: Pin](pingen: () => T) extends Bundle { withClockAndReset(clock, reset) { scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B) scl.o.oe := i2c.scl.oe - i2c.scl.in := SynchronizerShiftRegInit(scl.i.ival, syncStages, init = Bool(true)) + i2c.scl.in := SynchronizerShiftRegInit(scl.i.ival, syncStages, init = Bool(true), + name = Some("i2c_scl_sync")) sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B) sda.o.oe := i2c.sda.oe - i2c.sda.in := SynchronizerShiftRegInit(sda.i.ival, syncStages, init = Bool(true)) + i2c.sda.in := SynchronizerShiftRegInit(sda.i.ival, syncStages, init = Bool(true), + name = Some("i2c_sda_sync")) } } } diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala index f24cbad..01ae55c 100644 --- a/src/main/scala/devices/uart/UARTPeriphery.scala +++ b/src/main/scala/devices/uart/UARTPeriphery.scala @@ -51,7 +51,7 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle { withClockAndReset(clock, reset) { txd.outputPin(uart.txd) val rxd_t = rxd.inputPin() - uart.rxd := SynchronizerShiftRegInit(rxd_t, n = syncStages, init = Bool(true)) + uart.rxd := SynchronizerShiftRegInit(rxd_t, n = syncStages, init = Bool(true), name = Some("uart_rxd_sync")) } } }