From: Luke Kenneth Casson Leighton Date: Wed, 24 Oct 2018 03:50:56 +0000 (+0100) Subject: elwidth section X-Git-Tag: convert-csv-opcode-to-binary~4895 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=43a310cb9384f8ef4cbd8519bf3d26c367d2ed0c;p=libreriscv.git elwidth section --- diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 4adc449f0..7f5962063 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -1474,6 +1474,12 @@ where addw sign-extends. ### addw +The RV Specification specifically states that "W" variants of arithmetic +operations always produce 32-bit signed values. In a polymorphic +environment it is reasonable to assume that the signed aspect is +preserved, where it is the length of the operands and the result +that may be changed. + Standard Scalar RV64 (xlen): * RS1 @ xlen bits @@ -1496,10 +1502,9 @@ rs1 equals the bitwidth of rs2, no sign-extending will occur. It is only where the bitwidth of either rs1 or rs2 are different, will the lesser-width operand be sign-extended. -Effectively however, both rs1 and rs2 are being sign-extended to the -bitwidth of rd (or truncated), where for add they are both zero-extended. - -TODO +Effectively however, both rs1 and rs2 are being sign-extended (or truncated), +where for add they are both zero-extended. This holds true for all arithmetic +operations ending with "W". ### addiw