From: lkcl <lkcl@web>
Date: Thu, 13 Apr 2023 11:44:51 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls010_v1~11
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=43a67b82226bcc90420e686053202f80e8664da8;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls011.mdwn b/openpower/sv/rfc/ls011.mdwn
index ef2d03828..c19330eca 100644
--- a/openpower/sv/rfc/ls011.mdwn
+++ b/openpower/sv/rfc/ls011.mdwn
@@ -14,6 +14,16 @@ instructions are already present in x86 (sort-of).
 
 <https://azeria-labs.com/memory-instructions-load-and-store-part-4/>
 
+The LD/ST-Immediate-Post-Increment instructions are all Primary
+Opcode: there are 13 of these.  LD/ST-Indexed-Post-Increment
+are all effectively 9-bit XO and consequently may easily
+fit into one single Primary Opcode.  EXT2xx is recommended.
+
+One alternative idea is that bit 31 could be allocated (retrospectively)
+to Post-Increment.  Although it may be too late for Scalar Power ISA
+it **may** be possible to consider for SVP64Single and/or SVP64-Vector
+
+
 
 ```
 # LD/ST-Postincrement
@@ -36,6 +46,7 @@ stwup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 stwupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 stdup,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 stdupx,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+
 # FP LD/ST-Postincrement
 lfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
 lfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W
@@ -45,6 +56,25 @@ stfdu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 stfsu,    ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W
 stfdux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
 stfsux,   ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W
+
+# LD/ST-Shifted-Postincrement
+lbzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
+lhzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
+lhauspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
+lwzuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
+lwauspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
+lduspx,    ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
+stbuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
+sthuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
+stwuspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
+stduspx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
+
+# FP LD/ST-Shifted-Postincrement
+lfdupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
+lsdupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W
+stfdupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
+stfsupsx,   ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W
+
 ```
 
 # Example